DE69430982D1 - Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle - Google Patents

Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle

Info

Publication number
DE69430982D1
DE69430982D1 DE69430982T DE69430982T DE69430982D1 DE 69430982 D1 DE69430982 D1 DE 69430982D1 DE 69430982 T DE69430982 T DE 69430982T DE 69430982 T DE69430982 T DE 69430982T DE 69430982 D1 DE69430982 D1 DE 69430982D1
Authority
DE
Germany
Prior art keywords
pixel data
storage interface
representation storage
interleaving pixel
interleaving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430982T
Other languages
English (en)
Other versions
DE69430982T2 (de
Inventor
Bradley W Hoffert
Shawn F Storm
Robert Mark Stano
Olive, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69430982D1 publication Critical patent/DE69430982D1/de
Application granted granted Critical
Publication of DE69430982T2 publication Critical patent/DE69430982T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Memory System (AREA)
DE69430982T 1993-12-09 1994-11-23 Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle Expired - Fee Related DE69430982T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16431993A 1993-12-09 1993-12-09

Publications (2)

Publication Number Publication Date
DE69430982D1 true DE69430982D1 (de) 2002-08-22
DE69430982T2 DE69430982T2 (de) 2003-03-13

Family

ID=22593960

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430982T Expired - Fee Related DE69430982T2 (de) 1993-12-09 1994-11-23 Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle

Country Status (4)

Country Link
US (2) US5608427A (de)
EP (1) EP0658871B1 (de)
JP (1) JPH07219842A (de)
DE (1) DE69430982T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69430982T2 (de) * 1993-12-09 2003-03-13 Sun Microsystems, Inc. Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle
US5790138A (en) * 1996-01-16 1998-08-04 Monolithic System Technology, Inc. Method and structure for improving display data bandwidth in a unified memory architecture system
US5929868A (en) * 1996-09-27 1999-07-27 Apple Computer, Inc. Method and apparatus for computer display memory management
KR100248255B1 (ko) * 1997-05-16 2000-03-15 구본준 액정표시장치의 구동회로
US6008821A (en) * 1997-10-10 1999-12-28 International Business Machines Corporation Embedded frame buffer system and synchronization method
US6636222B1 (en) 1999-11-09 2003-10-21 Broadcom Corporation Video and graphics system with an MPEG video decoder for concurrent multi-row decoding
US6798420B1 (en) 1998-11-09 2004-09-28 Broadcom Corporation Video and graphics system with a single-port RAM
US6661422B1 (en) 1998-11-09 2003-12-09 Broadcom Corporation Video and graphics system with MPEG specific data transfer commands
EP1145218B1 (de) 1998-11-09 2004-05-19 Broadcom Corporation Anzeigesystem zur mischung von graphischen daten und videodaten
US7982740B2 (en) 1998-11-09 2011-07-19 Broadcom Corporation Low resolution graphics mode support using window descriptors
US7446774B1 (en) * 1998-11-09 2008-11-04 Broadcom Corporation Video and graphics system with an integrated system bridge controller
US6768774B1 (en) 1998-11-09 2004-07-27 Broadcom Corporation Video and graphics system with video scaling
US6853385B1 (en) * 1999-11-09 2005-02-08 Broadcom Corporation Video, audio and graphics decode, composite and display system
US6573905B1 (en) 1999-11-09 2003-06-03 Broadcom Corporation Video and graphics system with parallel processing of graphics windows
US9668011B2 (en) * 2001-02-05 2017-05-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Single chip set-top box system
US8913667B2 (en) 1999-11-09 2014-12-16 Broadcom Corporation Video decoding system having a programmable variable-length decoder
US6538656B1 (en) 1999-11-09 2003-03-25 Broadcom Corporation Video and graphics system with a data transport processor
KR100370239B1 (ko) 2000-10-25 2003-01-29 삼성전자 주식회사 고속 블럭 파이프라인 구조의 리드-솔로몬 디코더에적용하기 위한 메모리 장치와 메모리 액세스 방법 및 그메모리 장치를 구비한 리드-솔로몬 디코더
GB2380296B (en) * 2000-10-25 2003-09-10 Samsung Electronics Co Ltd Method of accessing memory device
JP3626144B2 (ja) * 2002-03-01 2005-03-02 株式会社セルシス 立体オブジェクトデータからの漫画的表現の２次元画像の生成方法および生成プログラム
JP2003323339A (ja) * 2002-03-01 2003-11-14 Sony Computer Entertainment Inc メモリアクセス装置、半導体デバイス、メモリアクセス制御方法、コンピュータプログラム及び記録媒体
US7667710B2 (en) * 2003-04-25 2010-02-23 Broadcom Corporation Graphics display system with line buffer control scheme
US8063916B2 (en) 2003-10-22 2011-11-22 Broadcom Corporation Graphics layer reduction for video composition
CN104932312A (zh) * 2015-06-10 2015-09-23 浪潮电子信息产业股份有限公司 一种板卡的制作方法及装置、pcb、板卡

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56156872A (en) * 1980-05-08 1981-12-03 Hitachi Ltd Character display unit
JPS59159196A (ja) * 1983-02-24 1984-09-08 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン グラフイツク・デイスプレイ・システム
US4742350A (en) * 1986-02-14 1988-05-03 International Business Machines Corporation Software managed video synchronization generation
US4716460A (en) * 1986-10-08 1987-12-29 Sperry Corporation Display refresh memory apparatus utilizing one half frame updating
US4910687A (en) * 1987-11-03 1990-03-20 International Business Machines Corporation Bit gating for efficient use of RAMs in variable plane displays
JPH01166127A (ja) * 1987-12-23 1989-06-30 Hitachi Ltd 画像表示方式
GB2219178A (en) * 1988-02-11 1989-11-29 Benchmark Technologies State machine controlled video processor
US4910683A (en) * 1988-12-20 1990-03-20 Sun Microsystems, Inc. Method and apparatus for fractional double buffering
US5014128A (en) * 1989-04-24 1991-05-07 Atronics International Inc. Video interface circuit for displaying capturing and mixing a live video image with computer graphics on a video monitor
DE69114825T2 (de) * 1990-12-21 1996-08-08 Sun Microsystems Inc Verfahren und Einrichtung zur Erhöhung der Verarbeitungsgeschwindigkeit eines Anzeigesystems mit Doppel-Pufferspeicher.
US5315700A (en) * 1992-02-18 1994-05-24 Neopath, Inc. Method and apparatus for rapidly processing data sequences
US5404318A (en) * 1992-12-01 1995-04-04 Sun Microsystems, Inc. Test mode readback in a memory display interface
DE69430982T2 (de) * 1993-12-09 2003-03-13 Sun Microsystems, Inc. Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle

Also Published As

Publication number Publication date
EP0658871B1 (de) 2002-07-17
JPH07219842A (ja) 1995-08-18
US5608427A (en) 1997-03-04
US5790136A (en) 1998-08-04
DE69430982T2 (de) 2003-03-13
EP0658871A2 (de) 1995-06-21
EP0658871A3 (de) 1997-01-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee