GB2380296B - Method of accessing memory device - Google Patents
Method of accessing memory deviceInfo
- Publication number
- GB2380296B GB2380296B GB0225260A GB0225260A GB2380296B GB 2380296 B GB2380296 B GB 2380296B GB 0225260 A GB0225260 A GB 0225260A GB 0225260 A GB0225260 A GB 0225260A GB 2380296 B GB2380296 B GB 2380296B
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory device
- accessing memory
- accessing
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1515—Reed-Solomon codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1555—Pipelined decoder implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6563—Implementations using multi-port memories
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Algebra (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0062904A KR100370239B1 (en) | 2000-10-25 | 2000-10-25 | Memory device for applying to high speed block pipelined reed-solomon decoder and method of memory access and reed-solomon decoder having the memory device |
GB0116275A GB2369215B (en) | 2000-10-25 | 2001-07-03 | Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0225260D0 GB0225260D0 (en) | 2002-12-11 |
GB2380296A GB2380296A (en) | 2003-04-02 |
GB2380296B true GB2380296B (en) | 2003-09-10 |
Family
ID=26246276
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0225260A Expired - Fee Related GB2380296B (en) | 2000-10-25 | 2001-07-03 | Method of accessing memory device |
GB0225258A Expired - Fee Related GB2379768B (en) | 2000-10-25 | 2001-07-03 | Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device |
GB0225261A Expired - Fee Related GB2380297B (en) | 2000-10-25 | 2001-07-03 | Reed-solomon decoder including memory device |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0225258A Expired - Fee Related GB2379768B (en) | 2000-10-25 | 2001-07-03 | Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device |
GB0225261A Expired - Fee Related GB2380297B (en) | 2000-10-25 | 2001-07-03 | Reed-solomon decoder including memory device |
Country Status (1)
Country | Link |
---|---|
GB (3) | GB2380296B (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995012850A1 (en) * | 1993-11-04 | 1995-05-11 | Cirrus Logic, Inc. | Reed-solomon decoder |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4725987A (en) * | 1985-10-23 | 1988-02-16 | Eastman Kodak Company | Architecture for a fast frame store using dynamic RAMS |
DE3715885A1 (en) * | 1987-05-13 | 1988-11-24 | Philips Patentverwaltung | INTERMEDIATE DEVICE, ESPECIALLY FOR A B-ISDN SWITCHING SYSTEM |
US4845713A (en) * | 1987-06-08 | 1989-07-04 | Exabyte Corporation | Method and apparatus for determining the coefficients of a locator polynomial |
DE69430982T2 (en) * | 1993-12-09 | 2003-03-13 | Sun Microsystems, Inc. | Interleaving pixel data for a representation storage interface |
US5506810A (en) * | 1994-08-16 | 1996-04-09 | Cirrus Logic, Inc. | Dual bank memory and systems using the same |
KR0170723B1 (en) * | 1995-12-29 | 1999-03-30 | 김광호 | Semiconductor memory device having duale bank |
US6081920A (en) * | 1998-01-08 | 2000-06-27 | Lsi Logic Corporation | Method and apparatus for fast decoding of a Reed-Solomon code |
-
2001
- 2001-07-03 GB GB0225260A patent/GB2380296B/en not_active Expired - Fee Related
- 2001-07-03 GB GB0225258A patent/GB2379768B/en not_active Expired - Fee Related
- 2001-07-03 GB GB0225261A patent/GB2380297B/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995012850A1 (en) * | 1993-11-04 | 1995-05-11 | Cirrus Logic, Inc. | Reed-solomon decoder |
US5446743A (en) * | 1993-11-04 | 1995-08-29 | Cirrus Logic, Inc. | Coefficient updating method and apparatus for Reed-Solomon decoder |
Also Published As
Publication number | Publication date |
---|---|
GB0225258D0 (en) | 2002-12-11 |
GB2380297B (en) | 2003-09-10 |
GB2380297A (en) | 2003-04-02 |
GB2379768A (en) | 2003-03-19 |
GB0225261D0 (en) | 2002-12-11 |
GB0225260D0 (en) | 2002-12-11 |
GB2380296A (en) | 2003-04-02 |
GB2379768B (en) | 2003-08-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20140703 |