GB9325747D0 - Data storage arrangement - Google Patents

Data storage arrangement

Info

Publication number
GB9325747D0
GB9325747D0 GB939325747A GB9325747A GB9325747D0 GB 9325747 D0 GB9325747 D0 GB 9325747D0 GB 939325747 A GB939325747 A GB 939325747A GB 9325747 A GB9325747 A GB 9325747A GB 9325747 D0 GB9325747 D0 GB 9325747D0
Authority
GB
United Kingdom
Prior art keywords
data storage
storage arrangement
arrangement
data
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB939325747A
Other versions
GB2284911A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Semiconductors Ltd
Original Assignee
Plessey Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Semiconductors Ltd filed Critical Plessey Semiconductors Ltd
Priority to GB9325747A priority Critical patent/GB2284911A/en
Publication of GB9325747D0 publication Critical patent/GB9325747D0/en
Publication of GB2284911A publication Critical patent/GB2284911A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
GB9325747A 1993-12-16 1993-12-16 Flexible lock-down cache. Withdrawn GB2284911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9325747A GB2284911A (en) 1993-12-16 1993-12-16 Flexible lock-down cache.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9325747A GB2284911A (en) 1993-12-16 1993-12-16 Flexible lock-down cache.

Publications (2)

Publication Number Publication Date
GB9325747D0 true GB9325747D0 (en) 1994-02-16
GB2284911A GB2284911A (en) 1995-06-21

Family

ID=10746705

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9325747A Withdrawn GB2284911A (en) 1993-12-16 1993-12-16 Flexible lock-down cache.

Country Status (1)

Country Link
GB (1) GB2284911A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11306084A (en) * 1998-04-23 1999-11-05 Fujitsu Ltd Information processor and storage medium
GB2385174B (en) 1999-01-19 2003-11-26 Advanced Risc Mach Ltd Memory control within data processing systems
EP1045307B1 (en) * 1999-04-16 2006-07-12 Infineon Technologies North America Corp. Dynamic reconfiguration of a micro-controller cache memory
US6868472B1 (en) * 1999-10-01 2005-03-15 Fujitsu Limited Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory
US6516384B1 (en) * 1999-12-30 2003-02-04 Intel Corporation Method and apparatus to perform a round robin and locking cache replacement scheme
KR100959133B1 (en) * 2003-07-01 2010-05-26 삼성전자주식회사 System and administration method for microprocessor with hot routine memory
US8069308B2 (en) 2008-02-13 2011-11-29 Honeywell International Inc. Cache pooling for computing systems
EP2261805B1 (en) * 2009-06-12 2013-07-31 Siemens Aktiengesellschaft Method for storing real time values
US11409643B2 (en) 2019-11-06 2022-08-09 Honeywell International Inc Systems and methods for simulating worst-case contention to determine worst-case execution time of applications executed on a processor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design

Also Published As

Publication number Publication date
GB2284911A (en) 1995-06-21

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)