DE69427512T2 - Direktspeicherzugriffssteuerung - Google Patents

Direktspeicherzugriffssteuerung

Info

Publication number
DE69427512T2
DE69427512T2 DE69427512T DE69427512T DE69427512T2 DE 69427512 T2 DE69427512 T2 DE 69427512T2 DE 69427512 T DE69427512 T DE 69427512T DE 69427512 T DE69427512 T DE 69427512T DE 69427512 T2 DE69427512 T2 DE 69427512T2
Authority
DE
Germany
Prior art keywords
memory access
access controller
direct memory
direct
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69427512T
Other languages
English (en)
Other versions
DE69427512D1 (de
Inventor
Douglas D Gephardt
Dan S Mdgett
James R Macdonald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69427512D1 publication Critical patent/DE69427512D1/de
Publication of DE69427512T2 publication Critical patent/DE69427512T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
DE69427512T 1993-10-29 1994-09-12 Direktspeicherzugriffssteuerung Expired - Lifetime DE69427512T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/145,376 US5561819A (en) 1993-10-29 1993-10-29 Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller

Publications (2)

Publication Number Publication Date
DE69427512D1 DE69427512D1 (de) 2001-07-26
DE69427512T2 true DE69427512T2 (de) 2002-04-25

Family

ID=22512829

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427512T Expired - Lifetime DE69427512T2 (de) 1993-10-29 1994-09-12 Direktspeicherzugriffssteuerung

Country Status (4)

Country Link
US (1) US5561819A (de)
EP (1) EP0651333B1 (de)
JP (1) JPH07182277A (de)
DE (1) DE69427512T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729762A (en) * 1995-04-21 1998-03-17 Intel Corporation Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
US5754806A (en) * 1995-11-03 1998-05-19 Holtek Microelectronics, Inc. Memory table look-up device and method
US5828900A (en) * 1996-01-03 1998-10-27 Intel Corporation International multiple-byte character generator support in application sharing which distinguishes guest keyboard input from host key board and bypassing execution of the generator module when guest keyboard input is determined
US5812798A (en) * 1996-01-26 1998-09-22 Motorola, Inc. Data processing system for accessing an external device and method therefore
US5809333A (en) * 1996-04-08 1998-09-15 Vlsi Technology, Inc. System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status
US6122669A (en) * 1997-02-14 2000-09-19 Advanced Micro Devices, Inc. Method and apparatus for auto-incrementing through table and updating single register in memory
US6055583A (en) * 1997-03-27 2000-04-25 Mitsubishi Semiconductor America, Inc. DMA controller with semaphore communication protocol
JPH10334037A (ja) * 1997-05-30 1998-12-18 Sanyo Electric Co Ltd 通信ｄｍａ装置
US6157970A (en) * 1997-09-24 2000-12-05 Intel Corporation Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
US6119189A (en) * 1997-09-24 2000-09-12 Intel Corporation Bus master transactions on a low pin count bus
US6047336A (en) * 1998-03-16 2000-04-04 International Business Machines Corporation Speculative direct memory access transfer between slave devices and memory
DE10047574C2 (de) * 2000-09-22 2003-07-17 Systemonic Ag Prozessorbusanordnung
US20070147115A1 (en) * 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7519754B2 (en) * 2005-12-28 2009-04-14 Silicon Storage Technology, Inc. Hard disk drive cache memory and playback device
US10360164B1 (en) * 2018-01-19 2019-07-23 Microchip Technology Incorporated Direct memory access adapter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4271466A (en) * 1975-02-20 1981-06-02 Panafacom Limited Direct memory access control system with byte/word control of data bus
US4514808A (en) * 1978-04-28 1985-04-30 Tokyo Shibaura Denki Kabushiki Kaisha Data transfer system for a data processing system provided with direct memory access units
JPS5789128A (en) * 1980-11-25 1982-06-03 Hitachi Ltd Controlling system for information interchange
US4815034A (en) * 1981-03-18 1989-03-21 Mackey Timothy I Dynamic memory address system for I/O devices
JPS6191752A (ja) * 1984-10-11 1986-05-09 Nec Corp マイクロコンピユ−タ
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
US5187783A (en) * 1989-03-15 1993-02-16 Micral, Inc. Controller for direct memory access
US5297242A (en) * 1989-12-15 1994-03-22 Nec Corporation DMA controller performing data transfer by 2-bus cycle transfer manner
JPH04363745A (ja) * 1991-05-17 1992-12-16 Toshiba Corp Ｄｍａコントローラ

Also Published As

Publication number Publication date
US5561819A (en) 1996-10-01
EP0651333B1 (de) 2001-06-20
JPH07182277A (ja) 1995-07-21
EP0651333A1 (de) 1995-05-03
DE69427512D1 (de) 2001-07-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY