DE69424530D1 - Synchronisieranordnung - Google Patents
SynchronisieranordnungInfo
- Publication number
- DE69424530D1 DE69424530D1 DE69424530T DE69424530T DE69424530D1 DE 69424530 D1 DE69424530 D1 DE 69424530D1 DE 69424530 T DE69424530 T DE 69424530T DE 69424530 T DE69424530 T DE 69424530T DE 69424530 D1 DE69424530 D1 DE 69424530D1
- Authority
- DE
- Germany
- Prior art keywords
- synchronization arrangement
- synchronization
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Databases & Information Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/235,647 US5497115A (en) | 1994-04-29 | 1994-04-29 | Flip-flop circuit having low standby power for driving synchronous dynamic random access memory |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69424530D1 true DE69424530D1 (de) | 2000-06-21 |
DE69424530T2 DE69424530T2 (de) | 2000-09-14 |
Family
ID=22886377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69424530T Expired - Lifetime DE69424530T2 (de) | 1994-04-29 | 1994-12-09 | Synchronisieranordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5497115A (de) |
EP (1) | EP0680049B1 (de) |
JP (1) | JP3357501B2 (de) |
KR (1) | KR0163485B1 (de) |
DE (1) | DE69424530T2 (de) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07307649A (ja) * | 1994-05-13 | 1995-11-21 | Fujitsu Ltd | 電子装置 |
US5729719A (en) * | 1994-09-07 | 1998-03-17 | Adaptec, Inc. | Synchronization circuit for clocked signals of similar frequencies |
US5796673A (en) | 1994-10-06 | 1998-08-18 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
EP0842578A4 (de) * | 1995-08-01 | 1998-12-09 | Auravision Corp | System zur synchronisation von videosignalen mit flankenphasenausrichtung |
JP3277112B2 (ja) * | 1996-01-31 | 2002-04-22 | 株式会社東芝 | 半導体記憶装置 |
US5825225A (en) * | 1996-02-09 | 1998-10-20 | Intel Corporation | Boosted differential latch |
US5838631A (en) | 1996-04-19 | 1998-11-17 | Integrated Device Technology, Inc. | Fully synchronous pipelined ram |
US5777501A (en) * | 1996-04-29 | 1998-07-07 | Mosaid Technologies Incorporated | Digital delay line for a reduced jitter digital delay lock loop |
US6002285A (en) * | 1996-05-28 | 1999-12-14 | International Business Machines Corporation | Circuitry and method for latching information |
US5646566A (en) * | 1996-06-21 | 1997-07-08 | International Business Machines Corporation | Low power clocked set/reset fast dynamic latch |
US5825224A (en) * | 1996-07-29 | 1998-10-20 | Sun Microsystems, Inc. | Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism |
US5796282A (en) * | 1996-08-12 | 1998-08-18 | Intel Corporation | Latching mechanism for pulsed domino logic with inherent race margin and time borrowing |
US5872736A (en) * | 1996-10-28 | 1999-02-16 | Micron Technology, Inc. | High speed input buffer |
US5917758A (en) * | 1996-11-04 | 1999-06-29 | Micron Technology, Inc. | Adjustable output driver circuit |
US5867049A (en) * | 1996-11-21 | 1999-02-02 | Sun Microsystems, Inc. | Zero setup time flip flop |
US5949254A (en) * | 1996-11-26 | 1999-09-07 | Micron Technology, Inc. | Adjustable output driver circuit |
US6115318A (en) | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
US5838177A (en) * | 1997-01-06 | 1998-11-17 | Micron Technology, Inc. | Adjustable output driver circuit having parallel pull-up and pull-down elements |
US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5956502A (en) * | 1997-03-05 | 1999-09-21 | Micron Technology, Inc. | Method and circuit for producing high-speed counts |
US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US5898638A (en) * | 1997-03-11 | 1999-04-27 | Micron Technology, Inc. | Latching wordline driver for multi-bank memory |
US5870347A (en) * | 1997-03-11 | 1999-02-09 | Micron Technology, Inc. | Multi-bank memory input/output line selection |
US6014759A (en) * | 1997-06-13 | 2000-01-11 | Micron Technology, Inc. | Method and apparatus for transferring test data from a memory array |
US6173432B1 (en) | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US6044429A (en) | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
KR19990031076A (ko) * | 1997-10-08 | 1999-05-06 | 윤종용 | 단일 펄스 발생 회로 |
US5949266A (en) * | 1997-10-28 | 1999-09-07 | Advanced Micro Devices, Inc. | Enhanced flip-flop for dynamic circuits |
US5986490A (en) * | 1997-12-18 | 1999-11-16 | Advanced Micro Devices, Inc. | Amplifier-based flip-flop elements |
US5923594A (en) * | 1998-02-17 | 1999-07-13 | Micron Technology, Inc. | Method and apparatus for coupling data from a memory device using a single ended read data path |
US6115320A (en) | 1998-02-23 | 2000-09-05 | Integrated Device Technology, Inc. | Separate byte control on fully synchronous pipelined SRAM |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
US6405280B1 (en) | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
US5986962A (en) * | 1998-07-23 | 1999-11-16 | International Business Machines Corporation | Internal shadow latch |
US6111444A (en) * | 1998-08-20 | 2000-08-29 | International Business Machines Corporation | Edge triggered latch |
TW419825B (en) | 1998-08-26 | 2001-01-21 | Toshiba Corp | Flip-flop circuit with clock signal control function and clock control signal |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
CA2250538A1 (en) | 1998-10-30 | 2000-04-30 | Mosaid Technologies Incorporated | Duty cycle regulator |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
KR100397890B1 (ko) * | 2001-07-04 | 2003-09-19 | 삼성전자주식회사 | 펄스 신호를 발생시키는 고속 입력 리시버 |
US6573775B2 (en) | 2001-10-30 | 2003-06-03 | Integrated Device Technology, Inc. | Integrated circuit flip-flops that utilize master and slave latched sense amplifiers |
US6700425B1 (en) | 2001-10-30 | 2004-03-02 | Integrated Device Technology, Inc. | Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
WO2005022746A1 (en) * | 2003-09-03 | 2005-03-10 | Koninklijke Philips Electronics N.V. | A static latch |
US7774499B1 (en) * | 2003-10-30 | 2010-08-10 | United Online, Inc. | Accelerating network communications |
WO2008114380A1 (ja) * | 2007-03-19 | 2008-09-25 | Fujitsu Limited | 記憶回路および記憶方法 |
US20110187414A1 (en) * | 2010-02-01 | 2011-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pbti tolerant circuit design |
US8659936B2 (en) * | 2010-07-06 | 2014-02-25 | Faraday Technology Corp. | Low power static random access memory |
US9729129B2 (en) * | 2014-12-05 | 2017-08-08 | Bhaskar Gopalan | System and method for reducing metastability in CMOS flip-flops |
KR102596875B1 (ko) * | 2016-11-23 | 2023-11-01 | 삼성전자주식회사 | 플립 플롭 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0810550B2 (ja) * | 1986-09-09 | 1996-01-31 | 日本電気株式会社 | バツフア回路 |
US4800296A (en) * | 1987-05-05 | 1989-01-24 | Texas Instruments Incorporated | Metastable defeating fli-flop |
US4980577A (en) * | 1987-06-18 | 1990-12-25 | Advanced Micro Devices, Inc. | Dual triggered edge-sensitive asynchrounous flip-flop |
US4970406A (en) * | 1987-12-30 | 1990-11-13 | Gazelle Microcircuits, Inc. | Resettable latch circuit |
US4845675A (en) * | 1988-01-22 | 1989-07-04 | Texas Instruments Incorporated | High-speed data latch with zero data hold time |
US5049760A (en) * | 1990-11-06 | 1991-09-17 | Motorola, Inc. | High speed complementary flipflop |
US5281865A (en) * | 1990-11-28 | 1994-01-25 | Hitachi, Ltd. | Flip-flop circuit |
US5124568A (en) * | 1991-02-14 | 1992-06-23 | Advanced Micro Devices, Inc. | Edge-triggered flip-flop |
-
1994
- 1994-04-29 US US08/235,647 patent/US5497115A/en not_active Expired - Lifetime
- 1994-12-09 DE DE69424530T patent/DE69424530T2/de not_active Expired - Lifetime
- 1994-12-09 EP EP94309206A patent/EP0680049B1/de not_active Expired - Lifetime
-
1995
- 1995-01-06 KR KR1019950000135A patent/KR0163485B1/ko not_active IP Right Cessation
- 1995-04-28 JP JP10642695A patent/JP3357501B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0680049A3 (de) | 1996-01-17 |
JPH08106786A (ja) | 1996-04-23 |
EP0680049B1 (de) | 2000-05-17 |
KR0163485B1 (ko) | 1999-03-20 |
US5497115A (en) | 1996-03-05 |
EP0680049A2 (de) | 1995-11-02 |
KR950035078A (ko) | 1995-12-30 |
JP3357501B2 (ja) | 2002-12-16 |
DE69424530T2 (de) | 2000-09-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP Owner name: MOSAID TECHNOLOGIES INCORPORATED, KANATA, ONTA, CA |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: PATENTANWAELTE CHARRIER RAPP & LIEBAU, 86152 AUGSB |