DE69418057D1 - Verbesserte maschenförmige geometrie für mos-gesteuerte halbleiteranordnungen - Google Patents
Verbesserte maschenförmige geometrie für mos-gesteuerte halbleiteranordnungenInfo
- Publication number
- DE69418057D1 DE69418057D1 DE69418057T DE69418057T DE69418057D1 DE 69418057 D1 DE69418057 D1 DE 69418057D1 DE 69418057 T DE69418057 T DE 69418057T DE 69418057 T DE69418057 T DE 69418057T DE 69418057 D1 DE69418057 D1 DE 69418057D1
- Authority
- DE
- Germany
- Prior art keywords
- mos
- shaped geometry
- controlled semiconductor
- semiconductor arrangements
- improved mesh
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/126—Power FETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/158,444 US5399892A (en) | 1993-11-29 | 1993-11-29 | Mesh geometry for MOS-gated semiconductor devices |
| PCT/US1994/013566 WO1995015008A1 (en) | 1993-11-29 | 1994-11-23 | Improved mesh geometry for mos-gated semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69418057D1 true DE69418057D1 (de) | 1999-05-27 |
| DE69418057T2 DE69418057T2 (de) | 1999-11-18 |
Family
ID=22568148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69418057T Expired - Fee Related DE69418057T2 (de) | 1993-11-29 | 1994-11-23 | Verbesserte maschenförmige geometrie für mos-gesteuerte halbleiteranordnungen |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5399892A (de) |
| EP (1) | EP0731985B1 (de) |
| JP (1) | JPH09505691A (de) |
| DE (1) | DE69418057T2 (de) |
| WO (1) | WO1995015008A1 (de) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5795793A (en) * | 1994-09-01 | 1998-08-18 | International Rectifier Corporation | Process for manufacture of MOS gated device with reduced mask count |
| US5595918A (en) * | 1995-03-23 | 1997-01-21 | International Rectifier Corporation | Process for manufacture of P channel MOS-gated device |
| KR100206555B1 (ko) * | 1995-12-30 | 1999-07-01 | 윤종용 | 전력용 트랜지스터 |
| EP0823735A1 (de) * | 1996-08-05 | 1998-02-11 | Sgs-Thomson Microelectronics S.A. | MOS-Technologie-Leistungsanordnung |
| KR100218260B1 (ko) * | 1997-01-14 | 1999-09-01 | 김덕중 | 트랜치 게이트형 모스트랜지스터의 제조방법 |
| KR100256109B1 (ko) * | 1997-05-07 | 2000-05-01 | 김덕중 | 전력 반도체 장치 |
| US6121089A (en) * | 1997-10-17 | 2000-09-19 | Intersil Corporation | Methods of forming power semiconductor devices having merged split-well body regions therein |
| US6144067A (en) * | 1998-11-23 | 2000-11-07 | International Rectifier Corp. | Strip gate poly structure for increased channel width and reduced gate resistance |
| JP4666708B2 (ja) | 1999-10-13 | 2011-04-06 | 新電元工業株式会社 | 電界効果トランジスタ |
| AU1211301A (en) * | 1999-10-22 | 2001-05-08 | Semiconductor Components Industries, L.L.C. | Semiconductor device with a single base region and method therefor |
| US6781194B2 (en) * | 2001-04-11 | 2004-08-24 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions and insulated trench-based electrodes therein |
| US6784486B2 (en) * | 2000-06-23 | 2004-08-31 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions therein |
| CN1520616A (zh) * | 2001-04-11 | 2004-08-11 | ��˹�������뵼�幫˾ | 具有防止基区穿通的横向延伸基区屏蔽区的功率半导体器件及其制造方法 |
| EP1387408A1 (de) | 2002-06-12 | 2004-02-04 | Motorola, Inc. | Leistungshalbleiteranordnung und Verfahren zu deren Herstellung |
| JP4396200B2 (ja) * | 2002-10-30 | 2010-01-13 | 株式会社デンソー | 半導体装置 |
| US8004049B2 (en) * | 2004-08-31 | 2011-08-23 | Freescale Semiconductor, Inc. | Power semiconductor device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3012185A1 (de) * | 1980-03-28 | 1981-10-08 | Siemens AG, 1000 Berlin und 8000 München | Feldeffekttransistor |
| US4677452A (en) * | 1981-10-26 | 1987-06-30 | Intersil, Inc. | Power field-effect transistor structures |
| US4644637A (en) * | 1983-12-30 | 1987-02-24 | General Electric Company | Method of making an insulated-gate semiconductor device with improved shorting region |
| FR2575334B1 (fr) * | 1984-12-21 | 1987-01-23 | Radiotechnique Compelec | Dispositif mos dont les regions de source sont disposees en bandes paralleles, et procede pour l'obtenir |
| US4833513A (en) * | 1985-01-20 | 1989-05-23 | Tdk Corporation | MOS FET semiconductor device having a cell pattern arrangement for optimizing channel width |
| US5262339A (en) * | 1989-06-12 | 1993-11-16 | Hitachi, Ltd. | Method of manufacturing a power semiconductor device using implants and solid diffusion source |
| US5288653A (en) * | 1991-02-27 | 1994-02-22 | Nec Corporation | Process of fabricating an insulated-gate field effect transistor |
| US5395776A (en) * | 1993-05-12 | 1995-03-07 | At&T Corp. | Method of making a rugged DMOS device |
-
1993
- 1993-11-29 US US08/158,444 patent/US5399892A/en not_active Expired - Lifetime
-
1994
- 1994-11-23 JP JP7515235A patent/JPH09505691A/ja not_active Ceased
- 1994-11-23 DE DE69418057T patent/DE69418057T2/de not_active Expired - Fee Related
- 1994-11-23 EP EP95904129A patent/EP0731985B1/de not_active Expired - Lifetime
- 1994-11-23 WO PCT/US1994/013566 patent/WO1995015008A1/en active IP Right Grant
-
1995
- 1995-01-04 US US08/368,612 patent/US5468668A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0731985B1 (de) | 1999-04-21 |
| US5468668A (en) | 1995-11-21 |
| DE69418057T2 (de) | 1999-11-18 |
| WO1995015008A1 (en) | 1995-06-01 |
| EP0731985A1 (de) | 1996-09-18 |
| US5399892A (en) | 1995-03-21 |
| JPH09505691A (ja) | 1997-06-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |