DE69408498D1 - Kodierung und Rekonstruktion des Dateninhaltes von bis zu zwei nichtverfügbaren DASDs in einer DASD-Anordnung - Google Patents
Kodierung und Rekonstruktion des Dateninhaltes von bis zu zwei nichtverfügbaren DASDs in einer DASD-AnordnungInfo
- Publication number
- DE69408498D1 DE69408498D1 DE69408498T DE69408498T DE69408498D1 DE 69408498 D1 DE69408498 D1 DE 69408498D1 DE 69408498 T DE69408498 T DE 69408498T DE 69408498 T DE69408498 T DE 69408498T DE 69408498 D1 DE69408498 D1 DE 69408498D1
- Authority
- DE
- Germany
- Prior art keywords
- array
- dasd
- data
- dasds
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
- G06F11/1092—Rebuilding, e.g. when physically replacing a failing disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US8570793A | 1993-06-30 | 1993-06-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69408498D1 true DE69408498D1 (de) | 1998-03-19 |
Family
ID=22193429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69408498T Expired - Lifetime DE69408498D1 (de) | 1993-06-30 | 1994-06-23 | Kodierung und Rekonstruktion des Dateninhaltes von bis zu zwei nichtverfügbaren DASDs in einer DASD-Anordnung |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0632376B1 (de) |
JP (1) | JP2750316B2 (de) |
DE (1) | DE69408498D1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6247157B1 (en) * | 1998-05-13 | 2001-06-12 | Intel Corporation | Method of encoding data signals for storage |
KR100472079B1 (ko) * | 2001-05-24 | 2005-02-21 | 에스케이케미칼주식회사 | 불소수지의 제조방법 |
JP4457019B2 (ja) | 2005-01-05 | 2010-04-28 | 富士通株式会社 | 情報処理システム及び一次ストレージ装置 |
JP4754852B2 (ja) | 2005-03-15 | 2011-08-24 | 富士通株式会社 | ストレージ制御装置および方法 |
JP2008197886A (ja) * | 2007-02-13 | 2008-08-28 | Nec Corp | ストレージ装置及びその制御方法 |
JP4499776B2 (ja) | 2007-10-31 | 2010-07-07 | 富士通株式会社 | ストレージ制御装置、方法、及びプログラム |
US8433979B2 (en) * | 2011-02-28 | 2013-04-30 | International Business Machines Corporation | Nested multiple erasure correcting codes for storage arrays |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5271012A (en) * | 1991-02-11 | 1993-12-14 | International Business Machines Corporation | Method and means for encoding and rebuilding data contents of up to two unavailable DASDs in an array of DASDs |
US5258984A (en) * | 1991-06-13 | 1993-11-02 | International Business Machines Corporation | Method and means for distributed sparing in DASD arrays |
EP0519669A3 (en) * | 1991-06-21 | 1994-07-06 | Ibm | Encoding and rebuilding data for a dasd array |
-
1994
- 1994-06-23 EP EP19940109687 patent/EP0632376B1/de not_active Expired - Lifetime
- 1994-06-23 DE DE69408498T patent/DE69408498D1/de not_active Expired - Lifetime
- 1994-06-24 JP JP6143535A patent/JP2750316B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0632376B1 (de) | 1998-02-11 |
JPH0728710A (ja) | 1995-01-31 |
EP0632376A2 (de) | 1995-01-04 |
EP0632376A3 (de) | 1995-03-01 |
JP2750316B2 (ja) | 1998-05-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |