DE69408075D1 - Vorrichtung zur Aktivierung einer Logikeinrichtung - Google Patents

Vorrichtung zur Aktivierung einer Logikeinrichtung

Info

Publication number
DE69408075D1
DE69408075D1 DE69408075T DE69408075T DE69408075D1 DE 69408075 D1 DE69408075 D1 DE 69408075D1 DE 69408075 T DE69408075 T DE 69408075T DE 69408075 T DE69408075 T DE 69408075T DE 69408075 D1 DE69408075 D1 DE 69408075D1
Authority
DE
Germany
Prior art keywords
activating
logic
logic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69408075T
Other languages
English (en)
Other versions
DE69408075T2 (de
Inventor
Jerry O Moench
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vantis Corp
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69408075D1 publication Critical patent/DE69408075D1/de
Application granted granted Critical
Publication of DE69408075T2 publication Critical patent/DE69408075T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/1659—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 to indicate that the value is within or outside a predetermined range of values (window)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/001—Arrangements for reducing power consumption in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Selective Calling Equipment (AREA)
DE69408075T 1993-10-08 1994-09-07 Vorrichtung zur Aktivierung einer Logikeinrichtung Expired - Fee Related DE69408075T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/134,523 US5418472A (en) 1993-10-08 1993-10-08 Input level detection circuit

Publications (2)

Publication Number Publication Date
DE69408075D1 true DE69408075D1 (de) 1998-02-26
DE69408075T2 DE69408075T2 (de) 1998-08-20

Family

ID=22463769

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69408075T Expired - Fee Related DE69408075T2 (de) 1993-10-08 1994-09-07 Vorrichtung zur Aktivierung einer Logikeinrichtung

Country Status (4)

Country Link
US (1) US5418472A (de)
EP (1) EP0647898B1 (de)
JP (1) JPH07236180A (de)
DE (1) DE69408075T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559465A (en) * 1994-07-29 1996-09-24 Cypress Semiconductor Corporation Output preconditioning circuit with an output level latch and a clamp
JP3741789B2 (ja) * 1996-08-30 2006-02-01 株式会社ルネサステクノロジ 電流バイパス回路付半導体集積回路
DE19706985B4 (de) 1997-02-21 2004-03-18 Telefonaktiebolaget L M Ericsson (Publ) Eingangspufferschaltkreis
TW367654B (en) * 1997-04-21 1999-08-21 Fujitsu Ltd Semiconductor device using complementary clock and signal input state detection circuit used for the same
US6104225A (en) 1997-04-21 2000-08-15 Fujitsu Limited Semiconductor device using complementary clock and signal input state detection circuit used for the same
IT1312287B1 (it) * 1999-05-03 2002-04-10 St Microelectronics Srl Circuito comparatore per segnali positivi e negativi,avente consumonullo,adatto per dispositivi a singola alimentazione positiva
TW457770B (en) * 2000-11-21 2001-10-01 Via Tech Inc Input/output pad apparatus with monitoring capability and its driving method
DE102007030569B4 (de) 2007-07-02 2012-11-08 Austriamicrosystems Ag Schaltungsanordnung und Verfahren zum Auswerten eines Datensignals
US8395923B2 (en) * 2008-12-30 2013-03-12 Intel Corporation Antifuse programmable memory array

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446381A (en) * 1982-04-22 1984-05-01 Zilog, Inc. Circuit and technique for initializing the state of bistable elements in an integrated electronic circuit
US4473759A (en) * 1982-04-22 1984-09-25 Motorola, Inc. Power sensing circuit and method
US4524291A (en) * 1983-01-06 1985-06-18 Motorola, Inc. Transition detector circuit
JPS59128822A (ja) * 1983-01-14 1984-07-25 Nec Corp 半導体回路
KR910009557B1 (ko) * 1987-03-31 1991-11-21 미쓰비시 뎅끼 가부시끼가이샤 동기신호 처리회로
US4902910A (en) * 1987-11-17 1990-02-20 Xilinx, Inc. Power supply voltage level sensing circuit
US4968902A (en) * 1989-08-02 1990-11-06 Tektronix, Inc. Unstable data recognition circuit for dual threshold synchronous data
US5097147A (en) * 1991-02-01 1992-03-17 Tektronix, Inc. Limited amplitude signal trigger circuit
US5214319A (en) * 1991-05-28 1993-05-25 Motorola, Inc. Monotonic pulse detector
JP2949980B2 (ja) * 1991-12-04 1999-09-20 富士通株式会社 電源制御装置及び情報処理装置

Also Published As

Publication number Publication date
EP0647898A1 (de) 1995-04-12
DE69408075T2 (de) 1998-08-20
EP0647898B1 (de) 1998-01-21
US5418472A (en) 1995-05-23
JPH07236180A (ja) 1995-09-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL

8339 Ceased/non-payment of the annual fee