DE69406140D1 - Verfahren zur verbesserung der rauschunempfindlichkeit eines phasenregelkreises und einrichtung, die ein solches verfahren verwendet - Google Patents
Verfahren zur verbesserung der rauschunempfindlichkeit eines phasenregelkreises und einrichtung, die ein solches verfahren verwendetInfo
- Publication number
- DE69406140D1 DE69406140D1 DE69406140T DE69406140T DE69406140D1 DE 69406140 D1 DE69406140 D1 DE 69406140D1 DE 69406140 T DE69406140 T DE 69406140T DE 69406140 T DE69406140 T DE 69406140T DE 69406140 D1 DE69406140 D1 DE 69406140D1
- Authority
- DE
- Germany
- Prior art keywords
- sensitivity
- noise
- improving
- control circuit
- phase control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9306836A FR2706229B1 (fr) | 1993-06-08 | 1993-06-08 | Procédé d'amélioration de l'immunité au bruit d'une boucle à verrouillage de phase et dispositif mettant en Óoeuvre ce procédé. |
PCT/FR1994/000659 WO1994029964A1 (fr) | 1993-06-08 | 1994-06-03 | Procede d'amelioration de l'immunite au bruit d'une boucle a verrouillage de phase et dispositif mettant en ×uvre ce procede |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69406140D1 true DE69406140D1 (de) | 1997-11-13 |
DE69406140T2 DE69406140T2 (de) | 1998-02-05 |
Family
ID=9447863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69406140T Expired - Fee Related DE69406140T2 (de) | 1993-06-08 | 1994-06-03 | Verfahren zur verbesserung der rauschunempfindlichkeit eines phasenregelkreises und einrichtung, die ein solches verfahren verwendet |
Country Status (6)
Country | Link |
---|---|
US (1) | US5663688A (de) |
EP (1) | EP0702862B1 (de) |
JP (1) | JPH09503629A (de) |
DE (1) | DE69406140T2 (de) |
FR (1) | FR2706229B1 (de) |
WO (1) | WO1994029964A1 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6014176A (en) * | 1995-06-21 | 2000-01-11 | Sony Corporation | Automatic phase control apparatus for phase locking the chroma burst of analog and digital video data using a numerically controlled oscillator |
KR100546541B1 (ko) * | 1995-08-14 | 2006-03-23 | 가부시끼가이샤 히다치 세이사꾸쇼 | Pll회로및영상재생장치 |
FR2742623B1 (fr) * | 1995-12-18 | 1998-03-06 | Sgs Thomson Microelectronics | Dispositif de traitement de signaux de synchronisation |
US5894081A (en) * | 1996-03-15 | 1999-04-13 | Intel Corporation | Method and apparatus for adjusting output signals from a semiconductor device to fulfill a timing specification |
JP3395818B2 (ja) * | 1996-04-19 | 2003-04-14 | ソニー株式会社 | Pll回路とそれを用いた信号処理装置 |
JP3669796B2 (ja) * | 1996-12-03 | 2005-07-13 | 富士通株式会社 | ディジタルpll回路 |
US5874846A (en) * | 1997-01-17 | 1999-02-23 | Chrontel Incorporated | Method and apparatus for frequency generation in a synchronous system |
JP3331894B2 (ja) * | 1997-01-30 | 2002-10-07 | ヤマハ株式会社 | Pll回路 |
US6026134A (en) * | 1997-06-19 | 2000-02-15 | Cypress Semiconductor Corp. | Phase locked loop (PLL) with linear parallel sampling phase detector |
DE19830260A1 (de) * | 1998-07-07 | 2000-01-13 | Alcatel Sa | Taktgenerator und Synchronisierungsverfahren |
US6072368A (en) * | 1998-10-21 | 2000-06-06 | International Business Machines Corporation | Phase locked loop unlock detector |
DE19908070C1 (de) * | 1999-02-12 | 2000-05-11 | Lear Automotive Electronics Gm | Verfahren zur Detektion der Horizontal- und Vertikalsynchronimpulse in einem Fernsehsignalempfänger und Schaltung zur Durchführung des Verfahrens |
DE60023833T2 (de) * | 1999-08-24 | 2006-07-20 | Koninklijke Philips Electronics N.V. | Phasenregelkreisschaltung mit einer ladungspumpe |
US20020070766A1 (en) * | 2000-12-11 | 2002-06-13 | Therisod Stefano G. | Signal detection scheme for data communication links |
KR100433526B1 (ko) * | 2001-09-28 | 2004-05-31 | 삼성전자주식회사 | 영상 처리를 위한 코스트 신호 발생 방법 및 장치 |
US7372928B1 (en) | 2002-11-15 | 2008-05-13 | Cypress Semiconductor Corporation | Method and system of cycle slip framing in a deserializer |
KR100532415B1 (ko) * | 2003-01-10 | 2005-12-02 | 삼성전자주식회사 | 돌발지터 정보를 차단할 수 있는 동기루프 회로 및 이의돌발지터 정보 차단방법 |
FR2864377B1 (fr) * | 2003-12-18 | 2006-08-18 | Eads Telecom | Boucle a asservissement de phase |
GB0804337D0 (en) | 2008-03-07 | 2008-04-16 | Cambridge Silicon Radio Ltd | Dual phase detector phase-locked loop |
CN101615906B (zh) * | 2008-10-28 | 2012-10-03 | 东莞理工学院 | 一种时钟同步数字锁相方法和装置 |
US8222961B2 (en) * | 2010-01-29 | 2012-07-17 | Huawei Technologies Co., Ltd. | Time-domain measurement of PLL bandwidth |
CN102281058B (zh) * | 2010-12-10 | 2014-03-12 | 华为技术有限公司 | 确定锁相环pll带宽特性的方法、装置和系统 |
WO2020038542A1 (en) * | 2018-08-20 | 2020-02-27 | Renesas Electronics Corporation | Oscillator frequency adjustment |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4047223A (en) * | 1976-01-16 | 1977-09-06 | Zenith Radio Corporation | Frequency scanning automatic phase control system |
US4287480A (en) * | 1980-01-10 | 1981-09-01 | Sperry Corporation | Phase locked loop out-of-lock detector |
US4435657A (en) * | 1981-02-27 | 1984-03-06 | Tokyo Shibaura Denki Kabushiki Kaisha | Phase detector circuit |
US4872155A (en) * | 1987-03-13 | 1989-10-03 | Pioneer Electronic Corporation | Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock |
US5008629A (en) * | 1988-06-20 | 1991-04-16 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer |
JPH071423B2 (ja) * | 1988-12-20 | 1995-01-11 | 株式会社山下電子設計 | パルス発生回路 |
US5028885A (en) * | 1990-08-30 | 1991-07-02 | Motorola, Inc. | Phase-locked loop signal generation system with control maintenance |
-
1993
- 1993-06-08 FR FR9306836A patent/FR2706229B1/fr not_active Expired - Lifetime
-
1994
- 1994-06-03 EP EP94918405A patent/EP0702862B1/de not_active Expired - Lifetime
- 1994-06-03 JP JP7501399A patent/JPH09503629A/ja active Pending
- 1994-06-03 US US08/553,376 patent/US5663688A/en not_active Expired - Fee Related
- 1994-06-03 DE DE69406140T patent/DE69406140T2/de not_active Expired - Fee Related
- 1994-06-03 WO PCT/FR1994/000659 patent/WO1994029964A1/fr active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
DE69406140T2 (de) | 1998-02-05 |
FR2706229A1 (fr) | 1994-12-16 |
EP0702862B1 (de) | 1997-10-08 |
US5663688A (en) | 1997-09-02 |
EP0702862A1 (de) | 1996-03-27 |
FR2706229B1 (fr) | 1996-08-02 |
WO1994029964A1 (fr) | 1994-12-22 |
JPH09503629A (ja) | 1997-04-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |