DE69330294D1 - Inter-hierarchisches Synchronisationssystem und LSI, das dieses System verwendet - Google Patents

Inter-hierarchisches Synchronisationssystem und LSI, das dieses System verwendet

Info

Publication number
DE69330294D1
DE69330294D1 DE69330294T DE69330294T DE69330294D1 DE 69330294 D1 DE69330294 D1 DE 69330294D1 DE 69330294 T DE69330294 T DE 69330294T DE 69330294 T DE69330294 T DE 69330294T DE 69330294 D1 DE69330294 D1 DE 69330294D1
Authority
DE
Germany
Prior art keywords
lsi
inter
hierarchical synchronization
synchronization system
hierarchical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69330294T
Other languages
English (en)
Other versions
DE69330294T2 (de
Inventor
Hajime Shiraishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69330294D1 publication Critical patent/DE69330294D1/de
Publication of DE69330294T2 publication Critical patent/DE69330294T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/35—Delay-insensitive circuit design, e.g. asynchronous or self-timed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Evolutionary Computation (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Multi Processors (AREA)
DE69330294T 1992-03-13 1993-03-12 Inter-hierarchisches Synchronisationssystem und LSI, das dieses System verwendet Expired - Fee Related DE69330294T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4055654A JP2791243B2 (ja) 1992-03-13 1992-03-13 階層間同期化システムおよびこれを用いた大規模集積回路

Publications (2)

Publication Number Publication Date
DE69330294D1 true DE69330294D1 (de) 2001-07-12
DE69330294T2 DE69330294T2 (de) 2001-09-20

Family

ID=13004830

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69330294T Expired - Fee Related DE69330294T2 (de) 1992-03-13 1993-03-12 Inter-hierarchisches Synchronisationssystem und LSI, das dieses System verwendet

Country Status (5)

Country Link
US (1) US5867691A (de)
EP (1) EP0560385B1 (de)
JP (1) JP2791243B2 (de)
KR (1) KR970003320B1 (de)
DE (1) DE69330294T2 (de)

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US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
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EP1329816B1 (de) * 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
JP3000961B2 (ja) * 1997-06-06 2000-01-17 日本電気株式会社 半導体集積回路
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
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US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
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US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
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JP3485885B2 (ja) * 2000-12-11 2004-01-13 三洋電機株式会社 半導体集積回路装置の設計方法
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
JP2002246471A (ja) * 2001-02-14 2002-08-30 Sony Corp 半導体装置
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US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
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US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
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US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
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US8281108B2 (en) * 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
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US20060075211A1 (en) * 2002-03-21 2006-04-06 Martin Vorbach Method and device for data processing
US8914590B2 (en) * 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) * 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
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US7394284B2 (en) * 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
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Also Published As

Publication number Publication date
JPH05259279A (ja) 1993-10-08
EP0560385A2 (de) 1993-09-15
EP0560385B1 (de) 2001-06-06
KR930020285A (ko) 1993-10-19
EP0560385A3 (en) 1994-07-06
JP2791243B2 (ja) 1998-08-27
KR970003320B1 (ko) 1997-03-17
DE69330294T2 (de) 2001-09-20
US5867691A (en) 1999-02-02

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Legal Events

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8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 MUENCHEN

8339 Ceased/non-payment of the annual fee