DE69523509D1 - Dezentralisiertes System und Mehrrechnersystem - Google Patents

Dezentralisiertes System und Mehrrechnersystem

Info

Publication number
DE69523509D1
DE69523509D1 DE69523509T DE69523509T DE69523509D1 DE 69523509 D1 DE69523509 D1 DE 69523509D1 DE 69523509 T DE69523509 T DE 69523509T DE 69523509 T DE69523509 T DE 69523509T DE 69523509 D1 DE69523509 D1 DE 69523509D1
Authority
DE
Germany
Prior art keywords
decentralized
computer system
computer
decentralized system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69523509T
Other languages
English (en)
Other versions
DE69523509T2 (de
Inventor
Masahiko Watanabe
Yasuo Morooka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE69523509D1 publication Critical patent/DE69523509D1/de
Publication of DE69523509T2 publication Critical patent/DE69523509T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
DE69523509T 1994-05-26 1995-05-25 Dezentralisiertes System und Mehrrechnersystem Expired - Fee Related DE69523509T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11244294 1994-05-26

Publications (2)

Publication Number Publication Date
DE69523509D1 true DE69523509D1 (de) 2001-12-06
DE69523509T2 DE69523509T2 (de) 2002-06-27

Family

ID=14586738

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69523509T Expired - Fee Related DE69523509T2 (de) 1994-05-26 1995-05-25 Dezentralisiertes System und Mehrrechnersystem

Country Status (5)

Country Link
US (1) US5696983A (de)
EP (1) EP0686921B1 (de)
KR (1) KR950035209A (de)
CN (1) CN1148215A (de)
DE (1) DE69523509T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6981069B2 (en) * 2001-06-25 2005-12-27 International Business Machines Corp. Compressed data transmission over a plurality of transmission paths
US7269491B2 (en) * 2002-05-16 2007-09-11 General Motors Corporation Cross-checking processors for powertrain control systems using a dedicated serial data link
BR0315624A (pt) 2002-10-22 2005-08-23 Jason A Sullivan Sistema de processamento em computador personalizável robusto
AU2003285949A1 (en) 2002-10-22 2004-05-13 Isys Technologies Non-peripherals processing control module having improved heat dissipating properties
CN102043446A (zh) 2002-10-22 2011-05-04 贾森·A·沙利文 用于提供动态模块处理单元的系统及方法
US7990724B2 (en) 2006-12-19 2011-08-02 Juhasz Paul R Mobile motherboard
JP6056509B2 (ja) * 2013-01-30 2017-01-11 富士通株式会社 情報処理装置および情報処理装置の制御方法
CN106154875B (zh) * 2015-05-27 2019-01-01 宁夏巨能机器人系统有限公司 一种用于关节机器人与上位机的通讯装置及其通讯方法
CN109993958B (zh) * 2019-05-08 2021-06-11 深圳市共济科技股份有限公司 一种rs485总线的数据采集系统及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH632365A5 (de) * 1978-01-30 1982-09-30 Patelhold Patentverwertung Datenaustauschverfahren zwischen mehreren partnern.
US4456965A (en) * 1980-10-14 1984-06-26 Texas Instruments Incorporated Data processing system having multiple buses
US4750111A (en) * 1984-08-22 1988-06-07 Crosby Jr Edward D Computer system for processing analog and digital data
US4760515A (en) * 1985-10-28 1988-07-26 International Business Machines Corporation Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
WO1988010468A1 (en) * 1987-06-19 1988-12-29 Human Devices, Inc. Multiply-installable, multi-processor board for personal computer and workstation expansion buses
US4912633A (en) * 1988-10-24 1990-03-27 Ncr Corporation Hierarchical multiple bus computer architecture
US5280591A (en) * 1991-07-22 1994-01-18 International Business Machines, Corporation Centralized backplane bus arbiter for multiprocessor systems

Also Published As

Publication number Publication date
CN1148215A (zh) 1997-04-23
KR950035209A (ko) 1995-12-30
EP0686921A3 (de) 1996-02-07
DE69523509T2 (de) 2002-06-27
EP0686921A2 (de) 1995-12-13
EP0686921B1 (de) 2001-10-31
US5696983A (en) 1997-12-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee