DE69326982D1 - Verfahren zur Bildung eines Lackmusters unter Verwendung einer optimierten Antireflexionsschicht. - Google Patents

Verfahren zur Bildung eines Lackmusters unter Verwendung einer optimierten Antireflexionsschicht.

Info

Publication number
DE69326982D1
DE69326982D1 DE69326982T DE69326982T DE69326982D1 DE 69326982 D1 DE69326982 D1 DE 69326982D1 DE 69326982 T DE69326982 T DE 69326982T DE 69326982 T DE69326982 T DE 69326982T DE 69326982 D1 DE69326982 D1 DE 69326982D1
Authority
DE
Germany
Prior art keywords
forming
reflective layer
optimized anti
paint pattern
paint
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69326982T
Other languages
English (en)
Other versions
DE69326982T2 (de
Inventor
Tohru Ogawa
Tetsuo Gocho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP35975092A external-priority patent/JP2897569B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69326982D1 publication Critical patent/DE69326982D1/de
Publication of DE69326982T2 publication Critical patent/DE69326982T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0275—Photolithographic processes using lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
DE1993626982 1992-08-20 1993-08-18 Verfahren zur Bildung eines Lackmusters unter Verwendung einer optimierten Antireflexionsschicht. Expired - Lifetime DE69326982T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24431492 1992-08-20
JP31607392 1992-10-31
JP35975092A JP2897569B2 (ja) 1991-12-30 1992-12-29 レジストパターン形成時に用いる反射防止膜の条件決定方法と、レジストパターン形成方法

Publications (2)

Publication Number Publication Date
DE69326982D1 true DE69326982D1 (de) 1999-12-16
DE69326982T2 DE69326982T2 (de) 2000-04-20

Family

ID=27333224

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1993626982 Expired - Lifetime DE69326982T2 (de) 1992-08-20 1993-08-18 Verfahren zur Bildung eines Lackmusters unter Verwendung einer optimierten Antireflexionsschicht.

Country Status (3)

Country Link
EP (2) EP0588087B1 (de)
DE (1) DE69326982T2 (de)
TW (2) TW349185B (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378659A (en) * 1993-07-06 1995-01-03 Motorola Inc. Method and structure for forming an integrated circuit pattern on a semiconductor substrate
JPH08255907A (ja) * 1995-01-18 1996-10-01 Canon Inc 絶縁ゲート型トランジスタ及びその製造方法
TW388083B (en) * 1995-02-20 2000-04-21 Hitachi Ltd Resist pattern-forming method using anti-reflective layer, resist pattern formed, and method of etching using resist pattern and product formed
US5918147A (en) * 1995-03-29 1999-06-29 Motorola, Inc. Process for forming a semiconductor device with an antireflective layer
US5968324A (en) * 1995-12-05 1999-10-19 Applied Materials, Inc. Method and apparatus for depositing antireflective coating
FR2749973B1 (fr) 1996-06-13 1998-09-25 France Telecom Procede de gravure de la grille en technologie mos utilisant un masque dur a base de sion
US6083852A (en) * 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6127262A (en) 1996-06-28 2000-10-03 Applied Materials, Inc. Method and apparatus for depositing an etch stop layer
US6156149A (en) * 1997-05-07 2000-12-05 Applied Materials, Inc. In situ deposition of a dielectric oxide layer and anti-reflective coating
US6562544B1 (en) 1996-11-04 2003-05-13 Applied Materials, Inc. Method and apparatus for improving accuracy in photolithographic processing of substrates
US6274292B1 (en) 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US6174810B1 (en) 1998-04-06 2001-01-16 Motorola, Inc. Copper interconnect structure and method of formation
US6268282B1 (en) 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6281100B1 (en) 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
JP2002530885A (ja) * 1998-11-25 2002-09-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 半導体製造における金属形状のパターニングのためのシランベース酸化物反射防止膜
US6828683B2 (en) 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US7235499B1 (en) 1999-01-20 2007-06-26 Micron Technology, Inc. Semiconductor processing methods
US7067414B1 (en) 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
US6440860B1 (en) 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
US6605394B2 (en) 2001-05-03 2003-08-12 Applied Materials, Inc. Organic bottom antireflective coating for high performance mask making using optical imaging
US6703169B2 (en) * 2001-07-23 2004-03-09 Applied Materials, Inc. Method of preparing optically imaged high performance photomasks
FR2985255B1 (fr) * 2011-12-28 2015-08-07 Ecole Polytech Article revetu d'un revetement interferentiel ayant des proprietes stables dans le temps.

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1534173A (fr) * 1966-08-10 1968-07-26 Gen Precision Inc Procédé pour former des réserves photographiques sur des supports transparents outranslucides avec une résolution élevée
JPS596540A (ja) * 1982-07-05 1984-01-13 Toshiba Corp 半導体装置の製造方法
US4451969A (en) * 1983-01-10 1984-06-05 Mobil Solar Energy Corporation Method of fabricating solar cells
JPH0255416A (ja) * 1988-08-19 1990-02-23 Seiko Epson Corp 半導体装置
EP0379604B1 (de) * 1989-01-23 1995-05-31 Siemens Aktiengesellschaft Verfahren zum Herstellen einer Siliziumnitridschicht, wie sie als Antireflexschicht in Photolithographieprozessen bei der Herstellung hochintegrierter Halbleiterschaltungen verwendet wird
JPH0712016B2 (ja) * 1989-12-26 1995-02-08 信越化学工業株式会社 Ｘ線リソグラフィー用ＳｉＣ膜の成膜方法
JP2895894B2 (ja) * 1989-12-27 1999-05-24 三洋電機株式会社 固体撮像素子の製造方法
JPH0456769A (ja) * 1990-06-22 1992-02-24 Nippon Steel Corp 微結晶を含有する非晶質炭化ケイ素膜の形成方法
JP2791525B2 (ja) * 1992-04-16 1998-08-27 三菱電機株式会社 反射防止膜の選定方法およびその方法により選定された反射防止膜

Also Published As

Publication number Publication date
EP0933683A2 (de) 1999-08-04
EP0588087A3 (de) 1995-08-02
DE69326982T2 (de) 2000-04-20
EP0933683A3 (de) 1999-12-15
EP0588087A2 (de) 1994-03-23
EP0588087B1 (de) 1999-11-10
TW349185B (en) 1999-01-01
TW363146B (en) 1999-07-01

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