DE69326236D1 - Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit - Google Patents

Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit

Info

Publication number
DE69326236D1
DE69326236D1 DE69326236T DE69326236T DE69326236D1 DE 69326236 D1 DE69326236 D1 DE 69326236D1 DE 69326236 T DE69326236 T DE 69326236T DE 69326236 T DE69326236 T DE 69326236T DE 69326236 D1 DE69326236 D1 DE 69326236D1
Authority
DE
Germany
Prior art keywords
memory
configuration unit
related configuration
nesting height
variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69326236T
Other languages
English (en)
Other versions
DE69326236T2 (de
Inventor
Antonio Grassi
Daniele Zanzottera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull Sas Les Clayes-Sous-Bois Fr
Original Assignee
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Italia SpA, Bull HN Information Systems Inc filed Critical Bull HN Information Systems Italia SpA
Application granted granted Critical
Publication of DE69326236D1 publication Critical patent/DE69326236D1/de
Publication of DE69326236T2 publication Critical patent/DE69326236T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
DE69326236T 1993-06-16 1993-06-16 Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit Expired - Lifetime DE69326236T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93830263A EP0629952B1 (de) 1993-06-16 1993-06-16 Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit

Publications (2)

Publication Number Publication Date
DE69326236D1 true DE69326236D1 (de) 1999-10-07
DE69326236T2 DE69326236T2 (de) 1999-12-30

Family

ID=8215184

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326236T Expired - Lifetime DE69326236T2 (de) 1993-06-16 1993-06-16 Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit

Country Status (3)

Country Link
US (1) US5668974A (de)
EP (1) EP0629952B1 (de)
DE (1) DE69326236T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59610672D1 (de) * 1995-12-29 2003-09-25 Siemens Ag Verfahren und Anordnung zum Konvertieren von Speicheradressen in Speicheransteuersignale
EP0782076A1 (de) * 1995-12-29 1997-07-02 Siemens Aktiengesellschaft Anordnung zum Ermitteln der Konfiguration eines Speichers
JPH10301842A (ja) * 1997-04-25 1998-11-13 Nec Corp メモリ制御装置
US6226720B1 (en) 1998-12-11 2001-05-01 International Business Machines Corporation Method for optimally configuring memory in a mixed interleave system
US6760822B2 (en) * 2001-03-30 2004-07-06 Intel Corporation Method and apparatus for interleaving data streams
US7017017B2 (en) * 2002-11-08 2006-03-21 Intel Corporation Memory controllers with interleaved mirrored memory modes
US7130229B2 (en) * 2002-11-08 2006-10-31 Intel Corporation Interleaved mirrored memory systems
KR100506448B1 (ko) * 2002-12-27 2005-08-08 주식회사 하이닉스반도체 불휘발성 강유전체 메모리를 이용한 인터리브 제어 장치
US6987470B2 (en) * 2003-11-21 2006-01-17 Qualcomm Incorporated Method to efficiently generate the row and column index for half rate interleaver in GSM
US7395401B2 (en) * 2005-09-30 2008-07-01 Sigmatel, Inc. System and methods for accessing solid-state memory devices
KR20080053527A (ko) 2005-12-16 2008-06-13 닛본 덴끼 가부시끼가이샤 기억 영역 할당 시스템 및 방법과 제어 장치
US7793059B2 (en) 2006-01-18 2010-09-07 Apple Inc. Interleaving policies for flash memory
JP5248482B2 (ja) * 2006-05-09 2013-07-31 シリコン ハイブ ビー・ヴィー プログラマブルデータ処理回路
US8886898B2 (en) * 2009-08-19 2014-11-11 Oracle America, Inc. Efficient interleaving between a non-power-of-two number of entities
US20110296078A1 (en) * 2010-06-01 2011-12-01 Qualcomm Incorporated Memory pool interface methods and apparatuses
US9256531B2 (en) 2012-06-19 2016-02-09 Samsung Electronics Co., Ltd. Memory system and SoC including linear addresss remapping logic
US9837132B2 (en) * 2013-09-24 2017-12-05 Rambus, Inc. High capacity memory system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280176A (en) * 1978-12-26 1981-07-21 International Business Machines Corporation Memory configuration, address interleaving, relocation and access control system
US4507730A (en) * 1981-10-01 1985-03-26 Honeywell Information Systems Inc. Memory system with automatic memory configuration
US4430727A (en) * 1981-11-10 1984-02-07 International Business Machines Corp. Storage element reconfiguration
US4788656A (en) * 1984-05-25 1988-11-29 The Johns Hopkins University Cache memory and pre-processor
US4783736A (en) * 1985-07-22 1988-11-08 Alliant Computer Systems Corporation Digital computer with multisection cache
IT1216085B (it) * 1988-03-15 1990-02-22 Honeywell Bull Spa Apparato di selezione veloce di memoria locale.
US5129069A (en) * 1989-01-24 1992-07-07 Zenith Data Systems Corporation Method and apparatus for automatic memory configuration by a computer
JPH0760413B2 (ja) * 1989-05-12 1995-06-28 インターナショナル・ビジネス・マシーンズ・コーポレーション メモリ・システム
US5269010A (en) * 1990-08-31 1993-12-07 Advanced Micro Devices, Inc. Memory control for use in a memory system incorporating a plurality of memory banks
US5341489A (en) * 1992-04-14 1994-08-23 Eastman Kodak Company Memory card with programmable interleaving

Also Published As

Publication number Publication date
US5668974A (en) 1997-09-16
EP0629952A1 (de) 1994-12-21
DE69326236T2 (de) 1999-12-30
EP0629952B1 (de) 1999-09-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL ITALIA S.P.A., PREGNANA MILANESE, MAILAND, IT

8327 Change in the person/name/address of the patent owner

Owner name: EUNICS S.P.A., PREGNANA MILANESE, MILANO, IT

8328 Change in the person/name/address of the agent

Representative=s name: HUBER & SCHUESSLER, 81825 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: EUTELIA S.P.A., AREZZO, IT

8327 Change in the person/name/address of the patent owner

Owner name: BULL SAS, LES CLAYES-SOUS-BOIS, FR