DE69322947D1 - DRAM mit variabler Wortleitungsauswahl - Google Patents
DRAM mit variabler WortleitungsauswahlInfo
- Publication number
- DE69322947D1 DE69322947D1 DE69322947T DE69322947T DE69322947D1 DE 69322947 D1 DE69322947 D1 DE 69322947D1 DE 69322947 T DE69322947 T DE 69322947T DE 69322947 T DE69322947 T DE 69322947T DE 69322947 D1 DE69322947 D1 DE 69322947D1
- Authority
- DE
- Germany
- Prior art keywords
- dram
- word line
- line selection
- variable word
- variable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4065—Low level details of refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/013,333 US5331601A (en) | 1993-02-04 | 1993-02-04 | DRAM variable row select |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69322947D1 true DE69322947D1 (de) | 1999-02-18 |
| DE69322947T2 DE69322947T2 (de) | 1999-09-09 |
Family
ID=21759428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69322947T Expired - Fee Related DE69322947T2 (de) | 1993-02-04 | 1993-11-09 | DRAM mit variabler Wortleitungsauswahl |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5331601A (de) |
| EP (1) | EP0609577B1 (de) |
| JP (1) | JPH06318393A (de) |
| KR (1) | KR100263273B1 (de) |
| DE (1) | DE69322947T2 (de) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5257233A (en) * | 1990-10-31 | 1993-10-26 | Micron Technology, Inc. | Low power memory module using restricted RAM activation |
| US5497355A (en) * | 1994-06-03 | 1996-03-05 | Intel Corporation | Synchronous address latching for memory arrays |
| US5696917A (en) | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
| JP2576425B2 (ja) * | 1994-10-27 | 1997-01-29 | 日本電気株式会社 | 強誘電体メモリ装置 |
| EP0745998B1 (de) * | 1995-05-31 | 2004-01-02 | United Memories, Inc. | Schaltung und Verfahren zum Zugriff auf Speicherzellen einer Speicheranordnung |
| US5623450A (en) * | 1995-09-08 | 1997-04-22 | International Business Machines Corporation | Conditional recharge for dynamic logic |
| KR100190373B1 (ko) * | 1996-02-08 | 1999-06-01 | 김영환 | 리드 패스를 위한 고속 동기식 메모리 장치 |
| JPH09306168A (ja) * | 1996-05-14 | 1997-11-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
| IL121044A (en) * | 1996-07-15 | 2000-09-28 | Motorola Inc | Dynamic memory device |
| JP4056173B2 (ja) | 1999-04-14 | 2008-03-05 | 富士通株式会社 | 半導体記憶装置および該半導体記憶装置のリフレッシュ方法 |
| US6570801B2 (en) * | 2000-10-27 | 2003-05-27 | Kabushiki Kaisha Toshiba | Semiconductor memory having refresh function |
| US6738861B2 (en) * | 2001-09-20 | 2004-05-18 | Intel Corporation | System and method for managing data in memory for reducing power consumption |
| US6608783B2 (en) | 2001-12-27 | 2003-08-19 | Infineon Technologies North America Corp. | Twisted bit-line compensation |
| US6570794B1 (en) | 2001-12-27 | 2003-05-27 | Infineon Technologies North America Corp. | Twisted bit-line compensation for DRAM having redundancy |
| US6603694B1 (en) * | 2002-02-05 | 2003-08-05 | Infineon Technologies North America Corp. | Dynamic memory refresh circuitry |
| US6618314B1 (en) | 2002-03-04 | 2003-09-09 | Cypress Semiconductor Corp. | Method and architecture for reducing the power consumption for memory devices in refresh operations |
| EP1408510A3 (de) * | 2002-05-17 | 2005-05-18 | Matsushita Electric Industrial Co., Ltd. | Speichersteuerungsapparat, Verfahren und Programm dazu |
| US6665224B1 (en) | 2002-05-22 | 2003-12-16 | Infineon Technologies Ag | Partial refresh for synchronous dynamic random access memory (SDRAM) circuits |
| US6862238B1 (en) | 2003-09-25 | 2005-03-01 | Infineon Technologies Ag | Memory system with reduced refresh current |
| US7099221B2 (en) * | 2004-05-06 | 2006-08-29 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
| US7116602B2 (en) * | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
| US7158434B2 (en) * | 2005-04-29 | 2007-01-02 | Infineon Technologies, Ag | Self-refresh circuit with optimized power consumption |
| US7894289B2 (en) * | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
| US7900120B2 (en) * | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
| CN109817257B (zh) * | 2018-12-27 | 2020-10-13 | 西安紫光国芯半导体有限公司 | 一种动态存储器刷新操作下的省电方法和动态存储器 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63152096A (ja) * | 1986-12-17 | 1988-06-24 | Hitachi Ltd | 半導体記憶装置 |
| JP2617779B2 (ja) * | 1988-08-31 | 1997-06-04 | 三菱電機株式会社 | 半導体メモリ装置 |
| EP0484760A3 (en) * | 1990-11-08 | 1992-07-15 | Kabushiki Kaisha Toshiba | Memory refresh control system upon connection of extension unit |
| US5148546A (en) * | 1991-04-22 | 1992-09-15 | Blodgett Greg A | Method and system for minimizing power demands on portable computers and the like by refreshing selected dram cells |
-
1993
- 1993-02-04 US US08/013,333 patent/US5331601A/en not_active Expired - Lifetime
- 1993-11-09 EP EP93203125A patent/EP0609577B1/de not_active Expired - Lifetime
- 1993-11-09 DE DE69322947T patent/DE69322947T2/de not_active Expired - Fee Related
-
1994
- 1994-02-03 KR KR1019940001963A patent/KR100263273B1/ko not_active IP Right Cessation
- 1994-02-04 JP JP6033139A patent/JPH06318393A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06318393A (ja) | 1994-11-15 |
| DE69322947T2 (de) | 1999-09-09 |
| US5331601A (en) | 1994-07-19 |
| KR100263273B1 (ko) | 2000-08-01 |
| EP0609577A2 (de) | 1994-08-10 |
| EP0609577B1 (de) | 1999-01-07 |
| KR940020414A (ko) | 1994-09-16 |
| EP0609577A3 (de) | 1995-07-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |