DE69317602D1 - Paritäts-und hochgeschwindigkeitsnormierungskreis für ein massivparalleles verarbeitungssystem - Google Patents

Paritäts-und hochgeschwindigkeitsnormierungskreis für ein massivparalleles verarbeitungssystem

Info

Publication number
DE69317602D1
DE69317602D1 DE69317602T DE69317602T DE69317602D1 DE 69317602 D1 DE69317602 D1 DE 69317602D1 DE 69317602 T DE69317602 T DE 69317602T DE 69317602 T DE69317602 T DE 69317602T DE 69317602 D1 DE69317602 D1 DE 69317602D1
Authority
DE
Germany
Prior art keywords
parity
shift register
processing element
processing
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69317602T
Other languages
English (en)
Other versions
DE69317602T2 (de
Inventor
Robert Grondalski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/825,515 external-priority patent/US5417470A/en
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE69317602D1 publication Critical patent/DE69317602D1/de
Application granted granted Critical
Publication of DE69317602T2 publication Critical patent/DE69317602T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17381Two dimensional, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
DE69317602T 1992-01-24 1993-01-22 Paritäts-und hochgeschwindigkeitsnormierungskreis für ein massivparalleles verarbeitungssystem Expired - Fee Related DE69317602T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US82690792A 1992-01-24 1992-01-24
US07/825,515 US5417470A (en) 1991-01-25 1992-01-24 Structural module for vehicle door
PCT/US1993/000571 WO1993015460A2 (en) 1992-01-24 1993-01-22 Databus parity and high speed normalization circuit for a massively parallel processing system

Publications (2)

Publication Number Publication Date
DE69317602D1 true DE69317602D1 (de) 1998-04-30
DE69317602T2 DE69317602T2 (de) 1998-10-01

Family

ID=27124914

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69317602T Expired - Fee Related DE69317602T2 (de) 1992-01-24 1993-01-22 Paritäts-und hochgeschwindigkeitsnormierungskreis für ein massivparalleles verarbeitungssystem

Country Status (3)

Country Link
EP (1) EP0577813B1 (de)
DE (1) DE69317602T2 (de)
WO (1) WO1993015460A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2337836B (en) * 1995-02-23 2000-01-19 Sony Uk Ltd Data processing systems

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380046A (en) * 1979-05-21 1983-04-12 Nasa Massively parallel processor computer
JPS5750049A (en) * 1980-09-09 1982-03-24 Toshiba Corp Shifting circuit
JPH0642237B2 (ja) * 1983-12-28 1994-06-01 株式会社日立製作所 並列処理装置
US4791641A (en) * 1986-09-15 1988-12-13 Thinking Machines Corporation Parallel processor error checking
US4905178A (en) * 1986-09-19 1990-02-27 Performance Semiconductor Corporation Fast shifter method and structure
DE3851005T2 (de) * 1987-06-01 1995-04-20 Applied Intelligent Syst Inc Paralleles Nachbarverarbeitungssystem und -Verfahren.
JPS648438A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Data processor
US5241490A (en) * 1992-01-06 1993-08-31 Intel Corporation Fully decoded multistage leading zero detector and normalization apparatus

Also Published As

Publication number Publication date
EP0577813B1 (de) 1998-03-25
WO1993015460A3 (en) 1994-01-20
EP0577813A1 (de) 1994-01-12
DE69317602T2 (de) 1998-10-01
WO1993015460A2 (en) 1993-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, 80538 MUENCHEN

8339 Ceased/non-payment of the annual fee