DE69230923T2 - Verfahren und System zur automatischen Herstellung von Netzwerkdiagrammen - Google Patents
Verfahren und System zur automatischen Herstellung von NetzwerkdiagrammenInfo
- Publication number
- DE69230923T2 DE69230923T2 DE69230923T DE69230923T DE69230923T2 DE 69230923 T2 DE69230923 T2 DE 69230923T2 DE 69230923 T DE69230923 T DE 69230923T DE 69230923 T DE69230923 T DE 69230923T DE 69230923 T2 DE69230923 T2 DE 69230923T2
- Authority
- DE
- Germany
- Prior art keywords
- automatic production
- network diagrams
- diagrams
- network
- automatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/10—Geometric CAD
- G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/12—Symbolic schematics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computer Networks & Wireless Communication (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3004367A JP2612967B2 (ja) | 1991-01-18 | 1991-01-18 | 網図自動生成方法及びそのシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69230923D1 DE69230923D1 (de) | 2000-05-25 |
DE69230923T2 true DE69230923T2 (de) | 2000-10-26 |
Family
ID=11582406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69230923T Expired - Fee Related DE69230923T2 (de) | 1991-01-18 | 1992-01-17 | Verfahren und System zur automatischen Herstellung von Netzwerkdiagrammen |
Country Status (5)
Country | Link |
---|---|
US (1) | US5416721A (de) |
EP (1) | EP0495517B1 (de) |
JP (1) | JP2612967B2 (de) |
KR (1) | KR960013363B1 (de) |
DE (1) | DE69230923T2 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04365162A (ja) * | 1991-06-13 | 1992-12-17 | Matsushita Electric Ind Co Ltd | 資源割当解析方法とスケジューリング方法およびそのシステム |
JPH0765040A (ja) * | 1993-08-24 | 1995-03-10 | Matsushita Electric Ind Co Ltd | 機能データインターフェース方法および機能データインターフェース装置 |
JP2972540B2 (ja) * | 1994-03-24 | 1999-11-08 | 松下電器産業株式会社 | Lsi自動設計システム及びlsi自動設計方法 |
DE4437744A1 (de) * | 1994-10-21 | 1996-04-25 | Test Plus Electronic Gmbh | Verfahren zum Auffinden und zur Darstellung von Schaltungselementen einer elektronischen Schaltung für die Funktionsprüfung der Schaltung |
JP3424997B2 (ja) * | 1995-01-31 | 2003-07-07 | 富士通株式会社 | 回路設計装置 |
US5805861A (en) * | 1995-08-29 | 1998-09-08 | Unisys Corporation | Method of stabilizing component and net names of integrated circuits in electronic design automation systems |
US5731983A (en) * | 1995-12-29 | 1998-03-24 | Nec Usa, Inc. | Method for synthesizing a sequential circuit |
US5864487A (en) * | 1996-11-19 | 1999-01-26 | Unisys Corporation | Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool |
US5980092A (en) * | 1996-11-19 | 1999-11-09 | Unisys Corporation | Method and apparatus for optimizing a gated clock structure using a standard optimization tool |
US6026220A (en) * | 1996-11-19 | 2000-02-15 | Unisys Corporation | Method and apparatus for incremntally optimizing a circuit design |
US5956256A (en) * | 1996-11-19 | 1999-09-21 | Unisys Corporation | Method and apparatus for optimizing a circuit design having multi-paths therein |
US5960184A (en) * | 1996-11-19 | 1999-09-28 | Unisys Corporation | Method and apparatus for providing optimization parameters to a logic optimizer tool |
US5802075A (en) * | 1997-01-16 | 1998-09-01 | Unisys Corporation | Distributed test pattern generation |
US5912820A (en) * | 1997-01-22 | 1999-06-15 | Unisys Corporation | Method and apparatus for distributing a clock tree within a hierarchical circuit design |
US6684376B1 (en) | 1997-01-27 | 2004-01-27 | Unisys Corporation | Method and apparatus for selecting components within a circuit design database |
US6718520B1 (en) | 1997-01-27 | 2004-04-06 | Unisys Corporation | Method and apparatus for selectively providing hierarchy to a circuit design |
US6516456B1 (en) | 1997-01-27 | 2003-02-04 | Unisys Corporation | Method and apparatus for selectively viewing nets within a database editor tool |
US6754879B1 (en) | 1997-01-27 | 2004-06-22 | Unisys Corporation | Method and apparatus for providing modularity to a behavioral description of a circuit design |
US7076410B1 (en) * | 1997-01-27 | 2006-07-11 | Unisys Corporation | Method and apparatus for efficiently viewing a number of selected components using a database editor tool |
US6701289B1 (en) | 1997-01-27 | 2004-03-02 | Unisys Corporation | Method and apparatus for using a placement tool to manipulate cell substitution lists |
US6910200B1 (en) | 1997-01-27 | 2005-06-21 | Unisys Corporation | Method and apparatus for associating selected circuit instances and for performing a group operation thereon |
US6708144B1 (en) | 1997-01-27 | 2004-03-16 | Unisys Corporation | Spreadsheet driven I/O buffer synthesis process |
US6247166B1 (en) * | 1998-06-25 | 2001-06-12 | International Business Machines Corporation | Method and apparatus for assembling array and datapath macros |
US6499129B1 (en) * | 1998-07-22 | 2002-12-24 | Circuit Semantics, Inc. | Method of estimating performance of integrated circuit designs |
US7000202B1 (en) * | 1998-07-22 | 2006-02-14 | Magma Design Automation, Inc. | Method of vector generation for estimating performance of integrated circuit designs |
US6539533B1 (en) * | 2000-06-20 | 2003-03-25 | Bae Systems Information And Electronic Systems Integration, Inc. | Tool suite for the rapid development of advanced standard cell libraries |
US6889370B1 (en) * | 2000-06-20 | 2005-05-03 | Unisys Corporation | Method and apparatus for selecting and aligning cells using a placement tool |
US6546532B1 (en) | 2000-06-20 | 2003-04-08 | Unisys Corporation | Method and apparatus for traversing and placing cells using a placement tool |
US6940832B2 (en) * | 2003-01-17 | 2005-09-06 | The Research Foundation Of The City University Of New York | Routing method for mobile infrastructureless network |
RU2470357C2 (ru) * | 2010-12-27 | 2012-12-20 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Юго-Западный государственный университет" (ЮЗГУ) | Устройство поиска нижней оценки размещения в полносвязных матричных системах при однонаправленной передаче информации |
RU2451334C1 (ru) * | 2011-03-15 | 2012-05-20 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Юго-Западный государственный университет" (ЮЗГУ) | Устройство для оценки степени загрузки каналов в системах с древовидной топологической организацией при направленной передаче информации |
IT202100000794A1 (it) | 2021-01-18 | 2022-07-18 | Silvano Tosti | Processo di combustione con aria trattata mediante sistemi a membrana e relativo apparato |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0623985B2 (ja) * | 1984-02-22 | 1994-03-30 | 株式会社日立製作所 | 論理図自動生成方法 |
JPS60205672A (ja) * | 1984-03-30 | 1985-10-17 | Hitachi Ltd | 論理回路図の論理シンボル配置方法 |
US5050091A (en) * | 1985-02-28 | 1991-09-17 | Electric Editor, Inc. | Integrated electric design system with automatic constraint satisfaction |
JPS61204775A (ja) * | 1985-03-07 | 1986-09-10 | Fujitsu Ltd | 回路図自動生成方法 |
US4918614A (en) * | 1987-06-02 | 1990-04-17 | Lsi Logic Corporation | Hierarchical floorplanner |
JPH0786883B2 (ja) * | 1988-09-09 | 1995-09-20 | 松下電器産業株式会社 | 網図または諭理回路図自動生成方法およびそのシステム |
US5111413A (en) * | 1989-03-24 | 1992-05-05 | Vantage Analysis Systems, Inc. | Computer-aided engineering |
DE69024515T2 (de) * | 1989-03-29 | 1996-05-15 | Hewlett Packard Co | Gerät zur Streckenmessung und -analyse zur Leistungsabschätzung von Software-Entwürfen |
-
1991
- 1991-01-18 JP JP3004367A patent/JP2612967B2/ja not_active Expired - Fee Related
-
1992
- 1992-01-13 US US07/819,227 patent/US5416721A/en not_active Expired - Lifetime
- 1992-01-16 KR KR1019920000560A patent/KR960013363B1/ko not_active IP Right Cessation
- 1992-01-17 EP EP92100762A patent/EP0495517B1/de not_active Expired - Lifetime
- 1992-01-17 DE DE69230923T patent/DE69230923T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0495517A3 (en) | 1993-01-13 |
KR960013363B1 (ko) | 1996-10-04 |
US5416721A (en) | 1995-05-16 |
DE69230923D1 (de) | 2000-05-25 |
EP0495517B1 (de) | 2000-04-19 |
KR920015223A (ko) | 1992-08-26 |
EP0495517A2 (de) | 1992-07-22 |
JPH04279974A (ja) | 1992-10-06 |
JP2612967B2 (ja) | 1997-05-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |