DE69129453D1 - MOSFET-Kanalstruktur und Verfahren zur Herstellung - Google Patents

MOSFET-Kanalstruktur und Verfahren zur Herstellung

Info

Publication number
DE69129453D1
DE69129453D1 DE69129453T DE69129453T DE69129453D1 DE 69129453 D1 DE69129453 D1 DE 69129453D1 DE 69129453 T DE69129453 T DE 69129453T DE 69129453 T DE69129453 T DE 69129453T DE 69129453 D1 DE69129453 D1 DE 69129453D1
Authority
DE
Germany
Prior art keywords
manufacture
channel structure
mosfet channel
mosfet
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69129453T
Other languages
English (en)
Other versions
DE69129453T2 (de
Inventor
Alberto Oscar Adan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69129453D1 publication Critical patent/DE69129453D1/de
Publication of DE69129453T2 publication Critical patent/DE69129453T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Thin Film Transistor (AREA)
DE1991629453 1991-05-21 1991-08-16 MOSFET-Kanalstruktur und Verfahren zur Herstellung Expired - Fee Related DE69129453T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11615591A JP2633104B2 (ja) 1991-05-21 1991-05-21 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69129453D1 true DE69129453D1 (de) 1998-06-25
DE69129453T2 DE69129453T2 (de) 1998-12-03

Family

ID=14680135

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1991629453 Expired - Fee Related DE69129453T2 (de) 1991-05-21 1991-08-16 MOSFET-Kanalstruktur und Verfahren zur Herstellung

Country Status (5)

Country Link
EP (1) EP0514602B1 (de)
JP (1) JP2633104B2 (de)
KR (1) KR100214297B1 (de)
DE (1) DE69129453T2 (de)
TW (1) TW201360B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799315A (ja) * 1993-06-22 1995-04-11 Motorola Inc 半導体デバイスの対向するドープ領域のインターフェースにおけるキャリア濃度を制御する方法
EP0696050B1 (de) * 1994-07-18 1998-10-14 STMicroelectronics S.r.l. Nicht-flüchtiger EPROM und Flash-EEPROM-Speicher und Verfahren zu seiner Herstellung
EP0707346A1 (de) * 1994-10-11 1996-04-17 Advanced Micro Devices, Inc. Verfahren zur Herstellung einer integrierten Schaltungsanordnung
US5593907A (en) * 1995-03-08 1997-01-14 Advanced Micro Devices Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices
US6333217B1 (en) 1999-05-14 2001-12-25 Matsushita Electric Industrial Co., Ltd. Method of forming MOSFET with channel, extension and pocket implants

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3279662D1 (en) * 1981-12-30 1989-06-01 Thomson Components Mostek Corp Triple diffused short channel device structure
US4597824A (en) * 1983-11-11 1986-07-01 Kabushiki Kaisha Toshiba Method of producing semiconductor device
JPH0834310B2 (ja) * 1987-03-26 1996-03-29 沖電気工業株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2633104B2 (ja) 1997-07-23
EP0514602B1 (de) 1998-05-20
JPH04343437A (ja) 1992-11-30
EP0514602A1 (de) 1992-11-25
TW201360B (de) 1993-03-01
DE69129453T2 (de) 1998-12-03
KR100214297B1 (ko) 1999-08-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee