DE69128987D1 - Gatterausgangsstruktur mit drei Zuständen, insbesondere für CMOS ICs - Google Patents

Gatterausgangsstruktur mit drei Zuständen, insbesondere für CMOS ICs

Info

Publication number
DE69128987D1
DE69128987D1 DE69128987T DE69128987T DE69128987D1 DE 69128987 D1 DE69128987 D1 DE 69128987D1 DE 69128987 T DE69128987 T DE 69128987T DE 69128987 T DE69128987 T DE 69128987T DE 69128987 D1 DE69128987 D1 DE 69128987D1
Authority
DE
Germany
Prior art keywords
states
state structure
gate state
cmos ics
ics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128987T
Other languages
English (en)
Other versions
DE69128987T2 (de
Inventor
David Moloney
Gianfranco Vai
Maurizio Zuffada
Giorgio Betti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, SGS Thomson Microelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69128987D1 publication Critical patent/DE69128987D1/de
Application granted granted Critical
Publication of DE69128987T2 publication Critical patent/DE69128987T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69128987T 1990-06-22 1991-06-17 Gatterausgangsstruktur mit drei Zuständen, insbesondere für CMOS ICs Expired - Fee Related DE69128987T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT02072890A IT1250908B (it) 1990-06-22 1990-06-22 Struttura di porta d'uscita a tre stati particolarmente per circuiti integrati cmos

Publications (2)

Publication Number Publication Date
DE69128987D1 true DE69128987D1 (de) 1998-04-09
DE69128987T2 DE69128987T2 (de) 1998-06-18

Family

ID=11171172

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128987T Expired - Fee Related DE69128987T2 (de) 1990-06-22 1991-06-17 Gatterausgangsstruktur mit drei Zuständen, insbesondere für CMOS ICs

Country Status (5)

Country Link
US (1) US5200653A (de)
EP (1) EP0465873B1 (de)
JP (1) JPH04239218A (de)
DE (1) DE69128987T2 (de)
IT (1) IT1250908B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4141886C1 (de) * 1991-12-18 1993-01-28 Siemens Ag, 8000 Muenchen, De
JP2978346B2 (ja) * 1992-11-30 1999-11-15 三菱電機株式会社 半導体集積回路装置の入力回路
US5399925A (en) * 1993-08-02 1995-03-21 Xilinx, Inc. High-speed tristate inverter
US6133754A (en) * 1998-05-29 2000-10-17 Edo, Llc Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)
GB2347567A (en) * 1999-03-05 2000-09-06 Sharp Kk CMOS level shifters and sense amplifiers
TW482954B (en) * 2000-11-10 2002-04-11 Via Tech Inc Internal operation method of chip set to reduce the power consumption

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5567235A (en) * 1978-11-14 1980-05-21 Nec Corp Output circuit
JPS57166713A (en) * 1981-04-08 1982-10-14 Nec Corp Output circuit
US4465945A (en) * 1982-09-03 1984-08-14 Lsi Logic Corporation Tri-state CMOS driver having reduced gate delay
JPS6125326A (ja) * 1984-07-16 1986-02-04 Nec Corp バツフア回路
JPS61100024A (ja) * 1984-10-23 1986-05-19 Toshiba Corp マスタスライス型半導体集積回路
JPS62194733A (ja) * 1986-02-21 1987-08-27 Hitachi Tobu Semiconductor Ltd トライ・ステ−ト・ゲ−ト
JPS63285025A (ja) * 1987-05-18 1988-11-22 Nec Corp ３ステ−ト出力回路
DE3904910A1 (de) * 1989-02-17 1990-08-23 Texas Instruments Deutschland Integrierte gegentakt-ausgangsstufe
JPH02222217A (ja) * 1989-02-22 1990-09-05 Toshiba Corp プログラマブル論理回路

Also Published As

Publication number Publication date
IT1250908B (it) 1995-04-21
JPH04239218A (ja) 1992-08-27
US5200653A (en) 1993-04-06
EP0465873B1 (de) 1998-03-04
EP0465873A1 (de) 1992-01-15
IT9020728A1 (it) 1991-12-22
DE69128987T2 (de) 1998-06-18
IT9020728A0 (it) 1990-06-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: STMICROELECTRONICS S.R.L., AGRATE BRIANZA, MAILAND

8339 Ceased/non-payment of the annual fee