DE69127773T2 - Vorrichtung zur echten LRU-Ersetzung - Google Patents

Vorrichtung zur echten LRU-Ersetzung

Info

Publication number
DE69127773T2
DE69127773T2 DE69127773T DE69127773T DE69127773T2 DE 69127773 T2 DE69127773 T2 DE 69127773T2 DE 69127773 T DE69127773 T DE 69127773T DE 69127773 T DE69127773 T DE 69127773T DE 69127773 T2 DE69127773 T2 DE 69127773T2
Authority
DE
Germany
Prior art keywords
lru
way
processor
operations
mru
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127773T
Other languages
English (en)
Other versions
DE69127773D1 (de
Inventor
Michael J Collins
Roger E Tipley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69127773D1 publication Critical patent/DE69127773D1/de
Publication of DE69127773T2 publication Critical patent/DE69127773T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
DE69127773T 1990-06-15 1991-06-14 Vorrichtung zur echten LRU-Ersetzung Expired - Fee Related DE69127773T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53902690A 1990-06-15 1990-06-15

Publications (2)

Publication Number Publication Date
DE69127773D1 DE69127773D1 (de) 1997-11-06
DE69127773T2 true DE69127773T2 (de) 1998-04-02

Family

ID=24149447

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127773T Expired - Fee Related DE69127773T2 (de) 1990-06-15 1991-06-14 Vorrichtung zur echten LRU-Ersetzung

Country Status (5)

Country Link
US (1) US5325511A (de)
EP (1) EP0461923B1 (de)
JP (1) JPH04233051A (de)
AT (1) ATE158882T1 (de)
DE (1) DE69127773T2 (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471605A (en) * 1992-08-27 1995-11-28 Intel Corporation Apparatus for updating a multi-way set associative cache memory status array
US5813028A (en) * 1993-10-12 1998-09-22 Texas Instruments Incorporated Cache read miss request invalidation prevention method
US5548742A (en) * 1994-08-11 1996-08-20 Intel Corporation Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory
US5594886A (en) * 1994-10-23 1997-01-14 Lsi Logic Corporation Pseudo-LRU cache memory replacement method and apparatus utilizing nodes
US5893921A (en) * 1995-02-10 1999-04-13 International Business Machines Corporation Method for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controller
US5652859A (en) * 1995-08-17 1997-07-29 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
US5897651A (en) * 1995-11-13 1999-04-27 International Business Machines Corporation Information handling system including a direct access set associative cache and method for accessing same
US5715427A (en) * 1996-01-26 1998-02-03 International Business Machines Corporation Semi-associative cache with MRU/LRU replacement
US5845320A (en) * 1996-04-29 1998-12-01 Micron Technology, Inc. Circuit and method to implement a least recently used cache set replacement technique
US5781924A (en) * 1996-09-30 1998-07-14 Sun Microsystems, Inc. Computer caching methods and apparatus
US5809528A (en) * 1996-12-24 1998-09-15 International Business Machines Corporation Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
US6078995A (en) * 1996-12-26 2000-06-20 Micro Magic, Inc. Methods and apparatus for true least recently used (LRU) bit encoding for multi-way associative caches
TW374873B (en) * 1997-06-30 1999-11-21 Hyundai Electronics Ind A high-performance LRU memory capable of supporting multiple ports
AU4238500A (en) 1999-04-13 2000-11-14 Richard J. Gagnon Method of obtaining an electronically-stored financial document
US20120179715A1 (en) 1999-04-13 2012-07-12 Mirror Imaging L.L.C. Method of Obtaining An Electronically-Stored Financial Document
US6430655B1 (en) * 2000-01-31 2002-08-06 Mips Technologies, Inc. Scratchpad RAM memory accessible in parallel to a primary cache
US6658545B1 (en) * 2000-02-16 2003-12-02 Lucent Technologies Inc. Passing internal bus data external to a completed system
US6446171B1 (en) 2000-03-02 2002-09-03 Mips Technologies, Inc. Method and apparatus for tracking and update of LRU algorithm using vectors
US6704843B1 (en) * 2000-10-26 2004-03-09 International Business Machines Corporation Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
US6604174B1 (en) 2000-11-10 2003-08-05 International Business Machines Corporation Performance based system and method for dynamic allocation of a unified multiport cache
US6587384B2 (en) * 2001-04-21 2003-07-01 Hewlett-Packard Development Company, L.P. Multi-function serial I/O circuit
US6950904B2 (en) * 2002-06-25 2005-09-27 Intel Corporation Cache way replacement technique
JP3953903B2 (ja) * 2002-06-28 2007-08-08 富士通株式会社 キャッシュメモリ装置、及び、参照履歴のビット誤り検出方法
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7873820B2 (en) * 2005-11-15 2011-01-18 Mips Technologies, Inc. Processor utilizing a loop buffer to reduce power consumption
US7562191B2 (en) * 2005-11-15 2009-07-14 Mips Technologies, Inc. Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
US7496771B2 (en) * 2005-11-15 2009-02-24 Mips Technologies, Inc. Processor accessing a scratch pad on-demand to reduce power consumption
US20070204139A1 (en) 2006-02-28 2007-08-30 Mips Technologies, Inc. Compact linked-list-based multi-threaded instruction graduation buffer
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US20080016326A1 (en) * 2006-07-14 2008-01-17 Mips Technologies, Inc. Latest producer tracking in an out-of-order processor, and applications thereof
US7370178B1 (en) * 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
US7657708B2 (en) * 2006-08-18 2010-02-02 Mips Technologies, Inc. Methods for reducing data cache access power in a processor using way selection bits
US7650465B2 (en) 2006-08-18 2010-01-19 Mips Technologies, Inc. Micro tag array having way selection bits for reducing data cache access power
US8032734B2 (en) 2006-09-06 2011-10-04 Mips Technologies, Inc. Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
US7647475B2 (en) * 2006-09-06 2010-01-12 Mips Technologies, Inc. System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
US8078846B2 (en) 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3949368A (en) * 1974-01-23 1976-04-06 Data General Corporation Automatic data priority technique
US4181937A (en) * 1976-11-10 1980-01-01 Fujitsu Limited Data processing system having an intermediate buffer memory
US4168541A (en) * 1978-09-25 1979-09-18 Sperry Rand Corporation Paired least recently used block replacement system
US4334289A (en) * 1980-02-25 1982-06-08 Honeywell Information Systems Inc. Apparatus for recording the order of usage of locations in memory
US4442488A (en) * 1980-05-05 1984-04-10 Floating Point Systems, Inc. Instruction cache memory system
US4467411A (en) * 1981-03-06 1984-08-21 International Business Machines Corporation Scheduling device operations in a buffered peripheral subsystem
US4464712A (en) * 1981-07-06 1984-08-07 International Business Machines Corporation Second level cache replacement method and apparatus
US4811203A (en) * 1982-03-03 1989-03-07 Unisys Corporation Hierarchial memory system with separate criteria for replacement and writeback without replacement
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
WO1984002799A1 (en) * 1982-12-30 1984-07-19 Ibm A hierarchical memory system including separate cache memories for storing data and instructions
US5091850A (en) * 1987-09-28 1992-02-25 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5113510A (en) * 1987-12-22 1992-05-12 Thinking Machines Corporation Method and apparatus for operating a cache memory in a multi-processor
US4996641A (en) * 1988-04-15 1991-02-26 Motorola, Inc. Diagnostic mode for a cache
US4967414A (en) * 1989-01-06 1990-10-30 International Business Machines Corp. LRU error detection using the collection of read and written LRU bits
US5125085A (en) * 1989-09-01 1992-06-23 Bull Hn Information Systems Inc. Least recently used replacement level generating apparatus and method

Also Published As

Publication number Publication date
EP0461923B1 (de) 1997-10-01
ATE158882T1 (de) 1997-10-15
EP0461923A3 (en) 1992-03-25
US5325511A (en) 1994-06-28
DE69127773D1 (de) 1997-11-06
EP0461923A2 (de) 1991-12-18
JPH04233051A (ja) 1992-08-21

Similar Documents

Publication Publication Date Title
DE69127773D1 (de) Vorrichtung zur echten LRU-Ersetzung
ES2111528T3 (es) Procedimiento y aparato para acelerar las instrucciones de ramificacion.
ATE156278T1 (de) Verfahren und vorrichtung zum ordnen und in warteschlangesetzen mehrerer speicherzugriffsanforderungen
ATE527599T1 (de) Cache-speicher mit blockvorausholung und dma
ATE165679T1 (de) Verfahren und anordnung zur verbesserung der datenspeicherungsgeschwindigkeit eines computersystems
CA2022656A1 (en) Translation look-aside buffer for a computer memory system
CA2088779A1 (en) Computer performance by simulated cache associativity
KR920003163A (ko) 캐시 액세스와 병렬로 메모리 액세스를 수행하는 프로세서 및 그것에 의해 이용되는 방법
EP0404369A3 (de) Verfahren zur Aufrechterhaltung der Cache-Speicherkohärenz in einem Mehrrechnersystem
DE68917325D1 (de) Verfahren und Vorrichtung zum Schreiben gegenseitiger verriegelter Variablen in einen integrierten Cachespeicher.
EP0343567A3 (de) Mehrprozessoranordnung und Cache-Speichervorrichtung zur Verwendung in dieser Anordnung
EP0251056A3 (de) Cache-Etikettenlookaside
EP1439460A3 (de) Vorrichtung und Verfahren zur Ungültigkeitserklärung von redundanten Eintragungen in einem Cachespeicher für Verzweigungszieladressen
DE69219433D1 (de) Virtueller Durchschreibcachespeicher Synonym-Adressierung und Cache-Ungültigkeitserklärungen
EP0285346A3 (de) Cache-Speichervorrichtung
NO20025623D0 (no) Fremgangsmåte og arrangement for inspeksjon
CA2034709A1 (en) System for controlling an internally-installed cache memory
ATE191803T1 (de) Datenverarbeitungssystem mit aufrechterhaltung der cachespeicherkohärenz unter verwendung eines snoopprotokolls
DE69116543T2 (de) Anordnung zur intelligenz-prüfung
EP0310446A3 (de) Verwaltungsverfahren für einen Cachespeicher
SE8901280L (sv) Skaft till skrivutrustning eller liknande
EP0401021A3 (de) Pufferspeicheranordnung mit Adressen zur Seitenbezeichnung und seiteninternen Adressen
EP0366323A3 (de) Warteschlange zur Duplikatetikettenspeicherinvalidation
SE7812636L (sv) Optiskt instrument
JPS5616984A (en) Paging processing system

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee