DE69126167D1 - Elektronisches Gerät für die parallele Korrektur von geschützten Datenströmen mit Fehlererkennung durch zyklisch redundante Prüfung - Google Patents

Elektronisches Gerät für die parallele Korrektur von geschützten Datenströmen mit Fehlererkennung durch zyklisch redundante Prüfung

Info

Publication number
DE69126167D1
DE69126167D1 DE69126167T DE69126167T DE69126167D1 DE 69126167 D1 DE69126167 D1 DE 69126167D1 DE 69126167 T DE69126167 T DE 69126167T DE 69126167 T DE69126167 T DE 69126167T DE 69126167 D1 DE69126167 D1 DE 69126167D1
Authority
DE
Germany
Prior art keywords
syndrome
error detection
correction
electronic device
data stream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126167T
Other languages
English (en)
Other versions
DE69126167T2 (de
Inventor
Sergio Salvitti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Italia SpA
Original Assignee
Alcatel Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Italia SpA filed Critical Alcatel Italia SpA
Application granted granted Critical
Publication of DE69126167D1 publication Critical patent/DE69126167D1/de
Publication of DE69126167T2 publication Critical patent/DE69126167T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)
DE69126167T 1990-04-13 1991-04-08 Elektronisches Gerät für die parallele Korrektur von geschützten Datenströmen mit Fehlererkennung durch zyklisch redundante Prüfung Expired - Fee Related DE69126167T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20039A IT1240298B (it) 1990-04-13 1990-04-13 Dispositivo elettronico per la correzione parallela di stringhe dati protette col rilevamento degli errori mediante codice ciclico

Publications (2)

Publication Number Publication Date
DE69126167D1 true DE69126167D1 (de) 1997-06-26
DE69126167T2 DE69126167T2 (de) 1997-12-04

Family

ID=11163331

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126167T Expired - Fee Related DE69126167T2 (de) 1990-04-13 1991-04-08 Elektronisches Gerät für die parallele Korrektur von geschützten Datenströmen mit Fehlererkennung durch zyklisch redundante Prüfung

Country Status (5)

Country Link
EP (1) EP0455992B1 (de)
AT (1) ATE153488T1 (de)
DE (1) DE69126167T2 (de)
ES (1) ES2103754T3 (de)
IT (1) IT1240298B (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2068105B1 (es) * 1992-11-30 1995-11-01 Alcatel Standard Electrica Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.
KR0147150B1 (ko) * 1995-06-29 1998-09-15 김주용 디코더를 이용한 순환 리던던시 체크 오류 검출 및 정정 장치

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3859630A (en) * 1973-01-29 1975-01-07 Burroughs Corp Apparatus for detecting and correcting errors in digital information organized into a parallel format by use of cyclic polynomial error detecting and correcting codes
US4498174A (en) * 1982-08-25 1985-02-05 Ael Microtel Limited Parallel cyclic redundancy checking circuit
US4665523A (en) * 1984-02-15 1987-05-12 Stanford University Method and means for error detection and correction in high speed data transmission codes
US4868828A (en) * 1987-10-05 1989-09-19 California Institute Of Technology Architecture for time or transform domain decoding of reed-solomon codes

Also Published As

Publication number Publication date
ES2103754T3 (es) 1997-10-01
IT9020039A1 (it) 1991-10-13
DE69126167T2 (de) 1997-12-04
EP0455992B1 (de) 1997-05-21
ATE153488T1 (de) 1997-06-15
IT1240298B (it) 1993-12-07
EP0455992A2 (de) 1991-11-13
EP0455992A3 (en) 1993-01-13
IT9020039A0 (it) 1990-04-13

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee