DE69125052T2 - Halbleiterspeichervorrichtung mit Redundanzschaltung - Google Patents
Halbleiterspeichervorrichtung mit RedundanzschaltungInfo
- Publication number
- DE69125052T2 DE69125052T2 DE69125052T DE69125052T DE69125052T2 DE 69125052 T2 DE69125052 T2 DE 69125052T2 DE 69125052 T DE69125052 T DE 69125052T DE 69125052 T DE69125052 T DE 69125052T DE 69125052 T2 DE69125052 T2 DE 69125052T2
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- redundancy circuit
- redundancy
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14343990 | 1990-06-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69125052D1 DE69125052D1 (de) | 1997-04-17 |
DE69125052T2 true DE69125052T2 (de) | 1997-09-25 |
Family
ID=15338729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69125052T Expired - Fee Related DE69125052T2 (de) | 1990-06-01 | 1991-05-31 | Halbleiterspeichervorrichtung mit Redundanzschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5255226A (de) |
EP (1) | EP0459521B1 (de) |
KR (1) | KR950010309B1 (de) |
DE (1) | DE69125052T2 (de) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2554816B2 (ja) * | 1992-02-20 | 1996-11-20 | 株式会社東芝 | 半導体記憶装置 |
US5404331A (en) * | 1993-07-30 | 1995-04-04 | Sgs-Thomson Microelectronics, Inc. | Redundancy element check in IC memory without programming substitution of redundant elements |
JP2776247B2 (ja) * | 1993-11-17 | 1998-07-16 | 日本電気株式会社 | 半導体集積回路及びその製造方法 |
US5841712A (en) * | 1996-09-30 | 1998-11-24 | Advanced Micro Devices, Inc. | Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device |
US6629190B2 (en) * | 1998-03-05 | 2003-09-30 | Intel Corporation | Non-redundant nonvolatile memory and method for sequentially accessing the nonvolatile memory using shift registers to selectively bypass individual word lines |
US6526470B1 (en) * | 1998-09-28 | 2003-02-25 | Cypress Semiconductor Corp. | Fifo bus-sizing, bus-matching datapath architecture |
US6310880B1 (en) | 2000-03-17 | 2001-10-30 | Silicon Aquarius, Inc. | Content addressable memory cells and systems and devices using the same |
DE10063684A1 (de) * | 2000-12-20 | 2002-07-18 | Infineon Technologies Ag | Schaltungsanordnung zur Ansteuerung einer programmierbaren Verbindung |
US6941493B2 (en) * | 2002-02-27 | 2005-09-06 | Sun Microsystems, Inc. | Memory subsystem including an error detection mechanism for address and control signals |
US20030163769A1 (en) * | 2002-02-27 | 2003-08-28 | Sun Microsystems, Inc. | Memory module including an error detection mechanism for address and control signals |
US6973613B2 (en) * | 2002-06-28 | 2005-12-06 | Sun Microsystems, Inc. | Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure |
US6996766B2 (en) * | 2002-06-28 | 2006-02-07 | Sun Microsystems, Inc. | Error detection/correction code which detects and corrects a first failing component and optionally a second failing component |
US6976194B2 (en) * | 2002-06-28 | 2005-12-13 | Sun Microsystems, Inc. | Memory/Transmission medium failure handling controller and method |
US7174486B2 (en) * | 2002-11-22 | 2007-02-06 | International Business Machines Corporation | Automation of fuse compression for an ASIC design system |
US6996686B2 (en) * | 2002-12-23 | 2006-02-07 | Sun Microsystems, Inc. | Memory subsystem including memory modules having multiple banks |
US7779285B2 (en) * | 2003-02-18 | 2010-08-17 | Oracle America, Inc. | Memory system including independent isolated power for each memory module |
US7530008B2 (en) | 2003-08-08 | 2009-05-05 | Sun Microsystems, Inc. | Scalable-chip-correct ECC scheme |
US7188296B1 (en) | 2003-10-30 | 2007-03-06 | Sun Microsystems, Inc. | ECC for component failures using Galois fields |
JP4732709B2 (ja) * | 2004-05-20 | 2011-07-27 | 株式会社半導体エネルギー研究所 | シフトレジスタ及びそれを用いた電子機器 |
US7937510B1 (en) * | 2005-02-01 | 2011-05-03 | Altera Corporation | Lempel Ziv compression architecture |
DE102006022072B4 (de) * | 2005-10-04 | 2008-04-03 | Qimonda Flash Gmbh & Co. Kg | Messschaltung und Leseverfahren für Speicherzellen |
US8595573B2 (en) * | 2006-12-03 | 2013-11-26 | Apple Inc. | Automatic defect management in memory devices |
KR101865954B1 (ko) * | 2012-09-21 | 2018-06-08 | 현대자동차주식회사 | 소음 저감을 위한 친환경 자동차의 인버터 제어 방법 |
CN113569517B (zh) * | 2021-06-29 | 2024-02-23 | 南方电网科学研究院有限责任公司 | 一种减小列冗余替换电路面积的电路及芯片 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62152050A (ja) * | 1985-12-26 | 1987-07-07 | Nec Corp | 半導体メモリ |
US4719601A (en) * | 1986-05-02 | 1988-01-12 | International Business Machine Corporation | Column redundancy for two port random access memory |
JPH0748316B2 (ja) * | 1988-05-30 | 1995-05-24 | 日本電気株式会社 | デュアルポートメモリ回路 |
-
1991
- 1991-05-31 DE DE69125052T patent/DE69125052T2/de not_active Expired - Fee Related
- 1991-05-31 EP EP91108972A patent/EP0459521B1/de not_active Expired - Lifetime
- 1991-06-01 KR KR1019910009111A patent/KR950010309B1/ko not_active IP Right Cessation
- 1991-06-03 US US07/709,565 patent/US5255226A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR950010309B1 (ko) | 1995-09-14 |
EP0459521B1 (de) | 1997-03-12 |
KR920001553A (ko) | 1992-01-30 |
US5255226A (en) | 1993-10-19 |
EP0459521A3 (en) | 1992-11-19 |
DE69125052D1 (de) | 1997-04-17 |
EP0459521A2 (de) | 1991-12-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8339 | Ceased/non-payment of the annual fee |