DE69122575D1 - Datenrundungsvorrichtung - Google Patents

Datenrundungsvorrichtung

Info

Publication number
DE69122575D1
DE69122575D1 DE69122575T DE69122575T DE69122575D1 DE 69122575 D1 DE69122575 D1 DE 69122575D1 DE 69122575 T DE69122575 T DE 69122575T DE 69122575 T DE69122575 T DE 69122575T DE 69122575 D1 DE69122575 D1 DE 69122575D1
Authority
DE
Germany
Prior art keywords
rounding device
data rounding
data
rounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69122575T
Other languages
English (en)
Other versions
DE69122575T2 (de
Inventor
Juri Tatsuro
Kadono Shinya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69122575D1 publication Critical patent/DE69122575D1/de
Publication of DE69122575T2 publication Critical patent/DE69122575T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49952—Sticky bit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Color Television Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
DE1991622575 1990-07-30 1991-07-29 Datenrundungsvorrichtung Expired - Fee Related DE69122575T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20212390A JP3199371B2 (ja) 1990-07-30 1990-07-30 丸め装置

Publications (2)

Publication Number Publication Date
DE69122575D1 true DE69122575D1 (de) 1996-11-14
DE69122575T2 DE69122575T2 (de) 1997-04-17

Family

ID=16452347

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1991622575 Expired - Fee Related DE69122575T2 (de) 1990-07-30 1991-07-29 Datenrundungsvorrichtung

Country Status (4)

Country Link
US (2) US5218563A (de)
EP (1) EP0469841B1 (de)
JP (1) JP3199371B2 (de)
DE (1) DE69122575T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05265709A (ja) * 1992-03-23 1993-10-15 Nec Corp 丸め演算回路
EP0578950A3 (en) * 1992-07-15 1995-11-22 Ibm Method and apparatus for converting floating-point pixel values to byte pixel values by table lookup
JP3103914B2 (ja) * 1992-08-21 2000-10-30 ソニー株式会社 データの丸め処理回路およびデータの復元回路
EP0671816B1 (de) * 1993-09-28 2000-03-29 Sony Corporation Gerät zur kodierung/dekodierung mit rundung auf ausschliesslich gerade oder ungerade werte
US5428567A (en) * 1994-05-09 1995-06-27 International Business Machines Corporation Memory structure to minimize rounding/trunction errors for n-dimensional image transformation
US5463575A (en) * 1994-06-24 1995-10-31 Rockwell International Corporation Reduced quantization noise from single-precision multiplier
US5729481A (en) * 1995-03-31 1998-03-17 International Business Machines Corporation Method and system of rounding for quadratically converging division or square root
US5633689A (en) * 1995-12-29 1997-05-27 Thomson Consumer Electronics, Inc. Apparatus for separating a digital composite video signal into components
US5696710A (en) * 1995-12-29 1997-12-09 Thomson Consumer Electronics, Inc. Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal
DE19642380A1 (de) * 1996-10-14 1998-04-16 Sp3D Chip Design Gmbh Verfahren zum Zuordnen einer Anzahl von Vergleichswerten zu einer größeren Anzahl von Urspungswerten
US5930159A (en) * 1996-10-17 1999-07-27 Samsung Electronics Co., Ltd Right-shifting an integer operand and rounding a fractional intermediate result to obtain a rounded integer result
JPH10233652A (ja) * 1997-02-20 1998-09-02 Mitsubishi Electric Corp 巡回形ディジタルフィルタ
EP0869432B1 (de) * 1997-04-01 2002-10-02 Matsushita Electric Industrial Co., Ltd. Multiplizierverfahren und Multiplizierschaltung
KR100253304B1 (ko) 1997-07-29 2000-04-15 김영환 레터박스필터링회로및방법
US5912909A (en) * 1997-10-14 1999-06-15 Ncr Corporation Method and apparatus for efficient implementation of checksum calculations
US6285796B1 (en) * 1997-11-03 2001-09-04 Intel Corporation Pseudo-fixed length image compression scheme
US6360204B1 (en) * 1998-04-24 2002-03-19 Sarnoff Corporation Method and apparatus for implementing rounding in decoding an audio signal
US6148317A (en) * 1998-08-14 2000-11-14 Qualcomm Incorporated Method and apparatus for compressing signals in a fixed point format without introducing a bias
US7047272B2 (en) * 1998-10-06 2006-05-16 Texas Instruments Incorporated Rounding mechanisms in processors
DE69824000T2 (de) * 1998-10-06 2005-06-09 Texas Instruments Inc., Dallas Rundungsmechanismus
US6243728B1 (en) * 1999-07-12 2001-06-05 Sony Corporation Of Japan Partitioned shift right logic circuit having rounding support
US6513055B1 (en) * 1999-10-29 2003-01-28 Visteon Global Technologies, Inc. Apparatus and method for data width reduction in automotive systems
US7035892B2 (en) 1999-12-10 2006-04-25 Broadcom Corporation Apparatus and method for reducing precision of data
GB0031771D0 (en) * 2000-12-29 2001-02-07 Lsi Logic Corp Bit reduction using dither,rounding and error feedback
US6529929B2 (en) * 2001-03-22 2003-03-04 Teleman Multimedia, Inc. Quantization device and method using prime number dividers
US20030163501A1 (en) * 2001-05-30 2003-08-28 Sony Corporation And Sony Electronics Inc. Implementation to avoid overflow in IIR filter
FI20011610A0 (fi) * 2001-08-07 2001-08-07 Nokia Corp Menetelmä ja laite jakolaskun suorittamiseksi
US7130876B2 (en) * 2001-11-30 2006-10-31 General Instrument Corporation Systems and methods for efficient quantization
JP2004301976A (ja) * 2003-03-31 2004-10-28 Nec Lcd Technologies Ltd 映像信号処理装置
TWI234389B (en) * 2003-10-30 2005-06-11 Sunplus Technology Co Ltd Image buffer memory system to reduce the discontinuous change of gray scale and method thereof
JP3852451B2 (ja) * 2004-03-15 2006-11-29 ソニー株式会社 情報信号記録装置および情報信号再生装置
US20050286380A1 (en) * 2004-06-24 2005-12-29 Cirrus Logic, Inc. Digital adaptive hysteresis system
US9146706B2 (en) * 2006-05-05 2015-09-29 Qualcomm Incorporated Controlled-precision iterative arithmetic logic unit
US9104479B2 (en) * 2011-12-07 2015-08-11 Arm Limited Apparatus and method for rounding a floating-point value to an integral floating-point value
EP3074946B1 (de) 2013-11-27 2018-10-17 Thomson Licensing Verfahren und vorrichtung zur quantisierung des gleitkommawerts eines pixels in einem bild
GB2575122B (en) 2018-06-29 2021-12-01 Imagination Tech Ltd Mapping an n-bit number to an m-bit number

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891837A (en) * 1972-07-03 1975-06-24 Drew E Sunstein Digital linearity and bias error compensating by adding an extra bit
US4149261A (en) * 1976-03-19 1979-04-10 Canon Kabushiki Kaisha Computer having circuitry for rounding-off insignificant digits
EP0112428B1 (de) * 1982-12-28 1987-08-12 International Business Machines Corporation Analog-Digital-Umwandler
US4589084A (en) * 1983-05-16 1986-05-13 Rca Corporation Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals
SE440300B (sv) * 1983-11-24 1985-07-22 Ellemtel Utvecklings Ab Forfarande for att i en samplad signal kompensera for trunkeringsfel samt anordning for utforande av forfarandet
US4722066A (en) * 1985-07-30 1988-01-26 Rca Corporation Digital signal overflow correction apparatus

Also Published As

Publication number Publication date
JPH0485621A (ja) 1992-03-18
US5329475A (en) 1994-07-12
DE69122575T2 (de) 1997-04-17
US5218563A (en) 1993-06-08
JP3199371B2 (ja) 2001-08-20
EP0469841A1 (de) 1992-02-05
EP0469841B1 (de) 1996-10-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee