DE69118419D1 - Halbleiterschaltung zum Verhindern von Störungen aufgrund von Geräuschen - Google Patents

Halbleiterschaltung zum Verhindern von Störungen aufgrund von Geräuschen

Info

Publication number
DE69118419D1
DE69118419D1 DE69118419T DE69118419T DE69118419D1 DE 69118419 D1 DE69118419 D1 DE 69118419D1 DE 69118419 T DE69118419 T DE 69118419T DE 69118419 T DE69118419 T DE 69118419T DE 69118419 D1 DE69118419 D1 DE 69118419D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
noise interference
preventing noise
preventing
interference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69118419T
Other languages
English (en)
Other versions
DE69118419T2 (de
Inventor
Hirokazu Yamazaki
Masanobu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69118419D1 publication Critical patent/DE69118419D1/de
Application granted granted Critical
Publication of DE69118419T2 publication Critical patent/DE69118419T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE69118419T 1990-01-19 1991-01-19 Halbleiterschaltung zum Verhindern von Störungen aufgrund von Geräuschen Expired - Fee Related DE69118419T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011577A JP2728533B2 (ja) 1990-01-19 1990-01-19 半導体装置

Publications (2)

Publication Number Publication Date
DE69118419D1 true DE69118419D1 (de) 1996-05-09
DE69118419T2 DE69118419T2 (de) 1996-08-22

Family

ID=11781771

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69118419T Expired - Fee Related DE69118419T2 (de) 1990-01-19 1991-01-19 Halbleiterschaltung zum Verhindern von Störungen aufgrund von Geräuschen

Country Status (5)

Country Link
US (1) US5149990A (de)
EP (1) EP0439310B1 (de)
JP (1) JP2728533B2 (de)
KR (1) KR940009079B1 (de)
DE (1) DE69118419T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152859A (ja) * 1991-11-27 1993-06-18 Mitsubishi Electric Corp 半導体装置
JPH0738408A (ja) * 1993-07-19 1995-02-07 Sharp Corp バッファ回路
US5550840A (en) * 1994-01-12 1996-08-27 Lsi Logic Corporation Noise suppression in large three state busses during test
US5519344A (en) * 1994-06-30 1996-05-21 Proebsting; Robert J. Fast propagation technique in CMOS integrated circuits
US5552725A (en) * 1994-08-05 1996-09-03 Advanced Micro Devices, Inc. Low power, slew rate insensitive power-on reset circuit
US5524096A (en) * 1995-06-29 1996-06-04 Micron Quantum Devices, Inc. Circuit for generating a delayed standby signal in response to an external standby command
US5926050A (en) * 1996-07-29 1999-07-20 Townsend And Townsend And Crew Llp Separate set/reset paths for time critical signals
US5929680A (en) * 1997-05-16 1999-07-27 Tritech Microelectronics International Ltd Short circuit reduced CMOS buffer circuit
JP2000188534A (ja) 1998-04-23 2000-07-04 Hewlett Packard Co <Hp> クロック・バッファ回路装置
US6154045A (en) * 1998-12-22 2000-11-28 Intel Corporation Method and apparatus for reducing signal transmission delay using skewed gates
US6552589B1 (en) * 1999-10-21 2003-04-22 International Business Machines Corporation Method and apparatus for process independent clock signal distribution
US6466074B2 (en) * 2001-03-30 2002-10-15 Intel Corporation Low skew minimized clock splitter
KR100380025B1 (ko) * 2001-04-18 2003-04-18 삼성전자주식회사 반도체 메모리 장치에 적용되는 입력 버퍼의 노이즈면역성 향상장치
DE102004054546B4 (de) * 2004-11-11 2011-06-22 Qimonda AG, 81739 Treiberschaltung
US7409659B2 (en) * 2004-11-12 2008-08-05 Agere Systems Inc. System and method for suppressing crosstalk glitch in digital circuits
KR101151102B1 (ko) * 2010-10-26 2012-06-01 에스케이하이닉스 주식회사 데이터 출력 드라이버 및 이를 구비한 집적 회로

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957525A (ja) * 1982-09-28 1984-04-03 Fujitsu Ltd Ｃｍｉｓ回路装置
US4567385A (en) * 1983-06-22 1986-01-28 Harris Corporation Power switched logic gates
JPS635553A (ja) * 1986-06-25 1988-01-11 Fujitsu Ltd バツフア回路
JPS63139425A (ja) * 1986-12-01 1988-06-11 Mitsubishi Electric Corp インバ−タ回路
JPH0289292A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 半導体メモリ

Also Published As

Publication number Publication date
JP2728533B2 (ja) 1998-03-18
KR940009079B1 (ko) 1994-09-29
EP0439310A2 (de) 1991-07-31
KR910014939A (ko) 1991-08-31
JPH03216012A (ja) 1991-09-24
US5149990A (en) 1992-09-22
EP0439310A3 (en) 1991-11-13
EP0439310B1 (de) 1996-04-03
DE69118419T2 (de) 1996-08-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee