DE69114759D1 - Verfahren zum Herstellen von Mehrlagen-Koplanarleiter/Isolatorschichten unter Verwendung von lichtempfindlichen Polyimiden. - Google Patents

Verfahren zum Herstellen von Mehrlagen-Koplanarleiter/Isolatorschichten unter Verwendung von lichtempfindlichen Polyimiden.

Info

Publication number
DE69114759D1
DE69114759D1 DE69114759T DE69114759T DE69114759D1 DE 69114759 D1 DE69114759 D1 DE 69114759D1 DE 69114759 T DE69114759 T DE 69114759T DE 69114759 T DE69114759 T DE 69114759T DE 69114759 D1 DE69114759 D1 DE 69114759D1
Authority
DE
Germany
Prior art keywords
insulator layers
making multilayer
photosensitive polyimides
coplanar conductor
multilayer coplanar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114759T
Other languages
English (en)
Other versions
DE69114759T2 (de
Inventor
John Edward Cronin
Carter Welling Kaanta
Rosemary Ann Previti-Kelly
James Gardner Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69114759D1 publication Critical patent/DE69114759D1/de
Publication of DE69114759T2 publication Critical patent/DE69114759T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Formation Of Insulating Films (AREA)
DE69114759T 1990-04-30 1991-04-13 Verfahren zum Herstellen von Mehrlagen-Koplanarleiter/Isolatorschichten unter Verwendung von lichtempfindlichen Polyimiden. Expired - Fee Related DE69114759T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/516,394 US5091289A (en) 1990-04-30 1990-04-30 Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositions

Publications (2)

Publication Number Publication Date
DE69114759D1 true DE69114759D1 (de) 1996-01-04
DE69114759T2 DE69114759T2 (de) 1996-06-20

Family

ID=24055379

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114759T Expired - Fee Related DE69114759T2 (de) 1990-04-30 1991-04-13 Verfahren zum Herstellen von Mehrlagen-Koplanarleiter/Isolatorschichten unter Verwendung von lichtempfindlichen Polyimiden.

Country Status (4)

Country Link
US (1) US5091289A (de)
EP (1) EP0455031B1 (de)
JP (1) JPH0770594B2 (de)
DE (1) DE69114759T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5217566A (en) * 1991-06-06 1993-06-08 Lsi Logic Corporation Densifying and polishing glass layers
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5514616A (en) * 1991-08-26 1996-05-07 Lsi Logic Corporation Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures
US5397863A (en) * 1991-09-13 1995-03-14 International Business Machines Corporation Fluorinated carbon polymer composites
US5310622A (en) * 1992-05-29 1994-05-10 Sgs-Thomson Microelectronics, Inc. Method of patterning a reflective surface in an integrated circuit
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5425337A (en) * 1992-11-19 1995-06-20 Izusu Ceramics Research Institute Co., Ltd. Pre-chamber type engine
US5869175A (en) * 1994-01-31 1999-02-09 Stmicroelectronics, Inc. Integrated circuit structure having two photoresist layers
US5486493A (en) * 1994-02-25 1996-01-23 Jeng; Shin-Puu Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
JP3469976B2 (ja) * 1995-10-19 2003-11-25 三菱電機株式会社 多層配線の形成方法
US5888896A (en) * 1996-06-27 1999-03-30 Micron Technology, Inc. Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component
US6143640A (en) * 1997-09-23 2000-11-07 International Business Machines Corporation Method of fabricating a stacked via in copper/polyimide beol
US6127721A (en) * 1997-09-30 2000-10-03 Siemens Aktiengesellschaft Soft passivation layer in semiconductor fabrication
KR100252049B1 (ko) * 1997-11-18 2000-04-15 윤종용 원자층 증착법에 의한 알루미늄층의 제조방법
US6265780B1 (en) * 1998-12-01 2001-07-24 United Microelectronics Corp. Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6107006A (en) * 1999-01-18 2000-08-22 Winbond Electronics Corp. Method for forming pattern
FR2789804B1 (fr) * 1999-02-17 2002-08-23 France Telecom Procede de gravure anisotrope par plasma gazeux d'un materiau polymere dielectrique organique et application a la microelectronique
US6803327B1 (en) 1999-04-05 2004-10-12 Taiwan Semiconductor Manufacturing Company Cost effective polymide process to solve passivation extrusion or damage and SOG delminates
US6509259B1 (en) * 1999-06-09 2003-01-21 Alliedsignal Inc. Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices
US6387810B2 (en) * 1999-06-28 2002-05-14 International Business Machines Corporation Method for homogenizing device parameters through photoresist planarization
US6313025B1 (en) * 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6882045B2 (en) * 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors
US6428942B1 (en) 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
US6869750B2 (en) * 1999-10-28 2005-03-22 Fujitsu Limited Structure and method for forming a multilayered structure
US6798073B2 (en) * 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same
WO2024143209A1 (ja) * 2022-12-28 2024-07-04 富士フイルム株式会社 積層体の製造方法、感光性樹脂組成物、及び、半導体部材の製造方法
WO2024143212A1 (ja) * 2022-12-28 2024-07-04 富士フイルム株式会社 積層体の製造方法、半導体部材の製造方法、感光性樹脂組成物、積層体、半導体部材、及び、樹脂組成物

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3060913D1 (en) * 1979-05-12 1982-11-11 Fujitsu Ltd Improvement in method of manufacturing electronic device having multilayer wiring structure
JPS5850417B2 (ja) * 1979-07-31 1983-11-10 富士通株式会社 半導体装置の製造方法
US4629777A (en) * 1983-05-18 1986-12-16 Ciba-Geigy Corporation Polyimides, a process for their preparation and their use
US4657832A (en) * 1983-05-18 1987-04-14 Ciba-Geigy Corporation Photosensitive polymers as coating materials
US4656116A (en) * 1983-10-12 1987-04-07 Ciba-Geigy Corporation Radiation-sensitive coating composition
EP0167051B1 (de) * 1984-06-29 1988-10-12 Siemens Aktiengesellschaft Thermostabiles, durch Bestrahlung vernetzbares Polymersystem auf der Basis von Bisphenolen und Epichlorhydrin sowie Verfahren zu seiner Verwendung
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
US4698295A (en) * 1984-11-16 1987-10-06 Ciba-Geigy Corporation Polyimides, a process for their preparation and their use, and tetracarboxylic acids and tetracarboxylic acid derivatives
US4621045A (en) * 1985-06-03 1986-11-04 Motorola, Inc. Pillar via process
US4665007A (en) * 1985-08-19 1987-05-12 International Business Machines Corporation Planarization process for organic filling of deep trenches
US4786569A (en) * 1985-09-04 1988-11-22 Ciba-Geigy Corporation Adhesively bonded photostructurable polyimide film
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4842991A (en) * 1987-07-31 1989-06-27 Texas Instruments Incorporated Self-aligned nonnested sloped via
US4997746A (en) * 1988-11-22 1991-03-05 Greco Nancy A Method of forming conductive lines and studs

Also Published As

Publication number Publication date
JPH0770594B2 (ja) 1995-07-31
DE69114759T2 (de) 1996-06-20
EP0455031A2 (de) 1991-11-06
EP0455031B1 (de) 1995-11-22
US5091289A (en) 1992-02-25
JPH04229638A (ja) 1992-08-19
EP0455031A3 (en) 1992-04-22

Similar Documents

Publication Publication Date Title
DE69114759D1 (de) Verfahren zum Herstellen von Mehrlagen-Koplanarleiter/Isolatorschichten unter Verwendung von lichtempfindlichen Polyimiden.
DE69114346D1 (de) Verfahren zum Herstellen von mehrlagigen koplanaren Leitungs-/Isolator-Schichten unter Verwendung von lichtempfindlichem Polyimid.
KR890007380A (ko) 미세패턴형성방법
KR890700465A (ko) 공동의 광 전도체와 그 제조 방법 및 장치
FI882009A (fi) Laite ja menetelmä monikerrosrainan muodostamiseksi
DE69025746D1 (de) Verfahren zum Auftragen keramischer Schichten
AT382557B (de) Mehrschichtiger schrumpffilm und verfahren zum herstellen desselben
DE68908419D1 (de) Verfahren zur bildung von loetverbindungen.
DE3586080D1 (de) Verfahren zum herstellen von gruenen mehrschicht-keramikfolien.
ATA365584A (de) Verfahren zur herstellung von 7-carboxymethoxyfuro-(3,4-c)-pyridinderivaten
KR850000781A (ko) 패턴 형성 방법
PT88754A (pt) Method of making three-layer paper
DE59103711D1 (de) Verfahren zur herstellung hellfarbiger pasten von alpha-sulfofettsäurealkylester-alkalimetallsalzen.
DE58904566D1 (de) Verfahren zur herstellung von substituierten 2-chlorpyridinen.
ATE319687T1 (de) Verfahren zur herstellung von substituierten pyridinen
KR860002864A (ko) 패턴 형성 방법
DE3381293D1 (de) Verfahren zum herstellen von anisotrop leitenden schichten.
IT8667286A0 (it) Tessuti decorativi e relativi metodo e apparecchiatura per la loro formazione
DE69223809D1 (de) Verfahren zur verbesserung der qualität von kohlenwasserstoffen
DE3884502D1 (de) Polydiacetylen-duennschicht-herstellungsverfahren.
DE3766635D1 (de) Verfahren zum praegen von filmen.
ATA120788A (de) Verfahren zum herstellen von elektrisch leitfähigen polymer-metallverbindungen
FI914505A0 (fi) Menetelmä ja laitteisto koristelaminaattilevyjen valmistamiseksi
DE69021159D1 (de) Verfahren zum immunochemischen Bestimmen von Haptenen.
DE68917840D1 (de) Verfahren zum Herstellen einer dielektrischen Schicht.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee