DE69032174D1 - Datenprozessor mit der Fähigkeit, zwei Befehle gleichzeitig auszuführen - Google Patents

Datenprozessor mit der Fähigkeit, zwei Befehle gleichzeitig auszuführen

Info

Publication number
DE69032174D1
DE69032174D1 DE69032174T DE69032174T DE69032174D1 DE 69032174 D1 DE69032174 D1 DE 69032174D1 DE 69032174 T DE69032174 T DE 69032174T DE 69032174 T DE69032174 T DE 69032174T DE 69032174 D1 DE69032174 D1 DE 69032174D1
Authority
DE
Germany
Prior art keywords
execute
ability
data processor
commands simultaneously
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032174T
Other languages
English (en)
Other versions
DE69032174T2 (de
Inventor
Makoto Hanawa
Tadahiko Nishimukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE69032174D1 publication Critical patent/DE69032174D1/de
Publication of DE69032174T2 publication Critical patent/DE69032174T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69032174T 1989-11-08 1990-11-07 Datenprozessor mit der Fähigkeit, zwei Befehle gleichzeitig auszuführen Expired - Fee Related DE69032174T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28887489 1989-11-08

Publications (2)

Publication Number Publication Date
DE69032174D1 true DE69032174D1 (de) 1998-04-30
DE69032174T2 DE69032174T2 (de) 1998-12-03

Family

ID=17735881

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032174T Expired - Fee Related DE69032174T2 (de) 1989-11-08 1990-11-07 Datenprozessor mit der Fähigkeit, zwei Befehle gleichzeitig auszuführen

Country Status (5)

Country Link
US (1) US5269007A (de)
EP (1) EP0427245B1 (de)
JP (1) JP2816248B2 (de)
KR (1) KR0178078B1 (de)
DE (1) DE69032174T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2834292B2 (ja) * 1990-08-15 1998-12-09 株式会社日立製作所 データ・プロセッサ
JP3105197B2 (ja) 1991-06-24 2000-10-30 株式会社日立製作所 除算回路及び除算方法
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
JP2539974B2 (ja) * 1991-11-20 1996-10-02 富士通株式会社 情報処理装置におけるレジスタの読出制御方式
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
DE69415126T2 (de) * 1993-10-21 1999-07-08 Sun Microsystems Inc Gegenflusspipelineprozessor
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5542059A (en) * 1994-01-11 1996-07-30 Exponential Technology, Inc. Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
JPH07219769A (ja) * 1994-02-07 1995-08-18 Mitsubishi Electric Corp マイクロプロセッサ
WO1995022102A1 (en) * 1994-02-08 1995-08-17 Meridian Semiconductor, Inc. Method and apparatus for simultaneously executing instructions in a pipelined microprocessor
US5685009A (en) * 1994-07-20 1997-11-04 Exponential Technology, Inc. Shared floating-point registers and register port-pairing in a dual-architecture CPU
US5481693A (en) * 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5619663A (en) * 1994-09-16 1997-04-08 Philips Electronics North America Corp. Computer instruction prefetch system
JP3543181B2 (ja) * 1994-11-09 2004-07-14 株式会社ルネサステクノロジ データ処理装置
US5649174A (en) * 1994-12-09 1997-07-15 Vlsi Technology Inc. Microprocessor with instruction-cycle versus clock-frequency mode selection
US5659785A (en) * 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
TW448403B (en) * 1995-03-03 2001-08-01 Matsushita Electric Ind Co Ltd Pipeline data processing device and method for executing multiple data processing data dependent relationship
JP2798121B2 (ja) * 1995-08-04 1998-09-17 日本電気株式会社 データ処理装置
JP3658072B2 (ja) * 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
US5790826A (en) * 1996-03-19 1998-08-04 S3 Incorporated Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes
US5870577A (en) * 1996-11-27 1999-02-09 International Business Machines, Corp. System and method for dispatching two instructions to the same execution unit in a single cycle
US5864341A (en) * 1996-12-09 1999-01-26 International Business Machines Corporation Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding
US6061780A (en) * 1997-01-24 2000-05-09 Texas Instruments Incorporated Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units
US6484253B1 (en) 1997-01-24 2002-11-19 Mitsubishi Denki Kabushiki Kaisha Data processor
US6260137B1 (en) * 1997-09-12 2001-07-10 Siemens Aktiengesellschaft Data processing unit with digital signal processing capabilities
US6366998B1 (en) 1998-10-14 2002-04-02 Conexant Systems, Inc. Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
JP3683248B2 (ja) * 2002-10-22 2005-08-17 富士通株式会社 情報処理装置及び情報処理方法
US8135975B2 (en) * 2007-03-09 2012-03-13 Analog Devices, Inc. Software programmable timing architecture

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028015B2 (ja) * 1980-08-28 1985-07-02 日本電気株式会社 情報処理装置
JPS6015746A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd デ−タ処理装置
GB8401807D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Pipelined data processing apparatus
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
JPH0810430B2 (ja) * 1986-11-28 1996-01-31 株式会社日立製作所 情報処理装置
CA1327080C (en) * 1987-05-26 1994-02-15 Yoshiko Yamaguchi Reduced instruction set computer (risc) type microprocessor
US5073855A (en) * 1989-06-30 1991-12-17 Bull Hn Information Systems Inc. Resource conflict detection method and apparatus included in a pipelined processing unit

Also Published As

Publication number Publication date
DE69032174T2 (de) 1998-12-03
JPH03218523A (ja) 1991-09-26
KR910010304A (ko) 1991-06-29
EP0427245B1 (de) 1998-03-25
KR0178078B1 (ko) 1999-05-15
EP0427245A2 (de) 1991-05-15
EP0427245A3 (en) 1992-01-29
US5269007A (en) 1993-12-07
JP2816248B2 (ja) 1998-10-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee