DE69022652D1 - Schaltung zur Phasenanpassung. - Google Patents

Schaltung zur Phasenanpassung.

Info

Publication number
DE69022652D1
DE69022652D1 DE69022652T DE69022652T DE69022652D1 DE 69022652 D1 DE69022652 D1 DE 69022652D1 DE 69022652 T DE69022652 T DE 69022652T DE 69022652 T DE69022652 T DE 69022652T DE 69022652 D1 DE69022652 D1 DE 69022652D1
Authority
DE
Germany
Prior art keywords
circuit
phase adjustment
adjustment
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69022652T
Other languages
English (en)
Other versions
DE69022652T2 (de
Inventor
Atsuki Taniguchi
Haruo Yamashita
Tomohiro Ishihara
Takaaki Wakisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69022652D1 publication Critical patent/DE69022652D1/de
Application granted granted Critical
Publication of DE69022652T2 publication Critical patent/DE69022652T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
DE69022652T 1989-07-21 1990-07-19 Schaltung zur Phasenanpassung. Expired - Fee Related DE69022652T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1189597A JP2536929B2 (ja) 1989-07-21 1989-07-21 位相整合回路

Publications (2)

Publication Number Publication Date
DE69022652D1 true DE69022652D1 (de) 1995-11-02
DE69022652T2 DE69022652T2 (de) 1996-03-21

Family

ID=16243982

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022652T Expired - Fee Related DE69022652T2 (de) 1989-07-21 1990-07-19 Schaltung zur Phasenanpassung.

Country Status (5)

Country Link
US (1) US5099477A (de)
EP (1) EP0409230B1 (de)
JP (1) JP2536929B2 (de)
CA (1) CA2021688C (de)
DE (1) DE69022652T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237554A (en) * 1989-12-27 1993-08-17 Sony Corporation Apparatus for generating clock signals for data reproduction
EP0491090B1 (de) * 1990-12-18 1997-03-12 ALCATEL BELL Naamloze Vennootschap Synchronisationsschaltung
US5341403A (en) * 1992-01-27 1994-08-23 Analog Devices, Incorporated Means to avoid data distortion in clock-synchronized signal sampling
JP2770656B2 (ja) * 1992-05-11 1998-07-02 ヤマハ株式会社 集積回路装置
US5448715A (en) * 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
EP0590212A1 (de) * 1992-09-30 1994-04-06 International Business Machines Corporation Synchronisationseinrichtung für ein synchrones Datenkommunikationssystem
US5329529A (en) * 1993-04-02 1994-07-12 Thomson Consumer Electronics, Inc. Digital data arbitration apparatus
US5367534A (en) * 1993-06-16 1994-11-22 Universal Data Systems, Inc. Synchronous flow control method
US5442658A (en) * 1993-09-07 1995-08-15 International Business Machines Corporation Synchronization apparatus for a synchronous data processing system
US5402453A (en) * 1994-01-21 1995-03-28 Panasonic Technologies, Inc. Apparatus and method for reliably clocking a signal with arbitrary phase
US5646564A (en) * 1994-09-02 1997-07-08 Xilinx, Inc. Phase-locked delay loop for clock correction
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
JPH0877103A (ja) * 1994-09-07 1996-03-22 Hitachi Ltd バス同期化方式及びこれを用いた装置，システム
JP3311517B2 (ja) * 1994-10-20 2002-08-05 富士通株式会社 位相比較型ビット同期確立回路
FR2731309A1 (fr) * 1995-03-01 1996-09-06 Trt Telecom Radio Electr Systeme de controle d'une chaine de transmission
WO1997006491A1 (en) * 1995-08-10 1997-02-20 International Business Machines Corporation Synchronizing logic avoiding metastability
US5578946A (en) * 1995-10-06 1996-11-26 Xilinx, Inc. Input synchronization mechanism for inside/outside clock
GB9720811D0 (en) * 1997-09-30 1997-12-03 Sgs Thomson Microelectronics Dual port buffer
US6128319A (en) * 1997-11-24 2000-10-03 Network Excellence For Enterprises Corp. Hybrid interface for packet data switching
JP3671782B2 (ja) * 1999-12-10 2005-07-13 富士通株式会社 信号位相調整回路
US6806755B1 (en) * 2001-04-23 2004-10-19 Quantum 3D Technique for glitchless switching of asynchronous clocks
GB2387516B (en) * 2002-04-11 2005-03-09 Cambridge Broadband Ltd Communication system
EP1798887B1 (de) * 2005-12-16 2010-04-21 STMicroelectronics (Research & Development) Limited Isochrone Synchronisierungseinrichtung
EP2097276B1 (de) * 2006-12-04 2013-09-11 MICHELIN Recherche et Technique S.A. Backdoor-datensynchronisation für ein mehrfachfernmesssystem

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1108349B (it) * 1978-04-04 1985-12-09 Cselt Centro Studi Lab Telecom Procedimento e dispositivo di sincronizzazione per trasmissione numeriche via satellite
JPS5625849A (en) * 1979-08-10 1981-03-12 Hitachi Ltd Coding system
NL183214C (nl) * 1980-01-31 1988-08-16 Philips Nv Inrichting voor het synchroniseren van de fase van een lokaal opgewekt kloksignaal met de fase van een ingangssignaal.
FR2482806A1 (fr) * 1980-05-19 1981-11-20 France Etat Procede et dispositif de synchronisation de signal numerique
JPS60182833A (ja) * 1984-02-10 1985-09-18 プライム・コンピユータ・インコーポレイテツド リング形式データ通信回路網におけるクロツク回復装置
JPS62120744A (ja) * 1985-11-20 1987-06-02 Fujitsu Ltd Ｐｃｍ伝送符号化方式
US4782499A (en) * 1986-09-29 1988-11-01 Rockwell International Corporation Automatic alignment of a synchronous data system using a local reference clock and external clock with an unknown delay between the two clocks
US4806934A (en) * 1987-04-20 1989-02-21 Raytheon Company Tracking circuit for following objects through antenna nulls
DE3874458D1 (de) * 1987-08-06 1992-10-15 Landis & Gyr Betriebs Ag Anordnung zur umwandlung eines elektrischen mehrphasensignals in eine frequenz.

Also Published As

Publication number Publication date
CA2021688A1 (en) 1991-01-22
CA2021688C (en) 1993-11-02
JP2536929B2 (ja) 1996-09-25
EP0409230A2 (de) 1991-01-23
US5099477A (en) 1992-03-24
EP0409230B1 (de) 1995-09-27
JPH0353729A (ja) 1991-03-07
DE69022652T2 (de) 1996-03-21
EP0409230A3 (en) 1991-10-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee