DE69010598T2 - Dickschicht-Substrat auf metallischer Grundlage mit hoher thermischer Leitfähigkeit. - Google Patents
Dickschicht-Substrat auf metallischer Grundlage mit hoher thermischer Leitfähigkeit.Info
- Publication number
- DE69010598T2 DE69010598T2 DE69010598T DE69010598T DE69010598T2 DE 69010598 T2 DE69010598 T2 DE 69010598T2 DE 69010598 T DE69010598 T DE 69010598T DE 69010598 T DE69010598 T DE 69010598T DE 69010598 T2 DE69010598 T2 DE 69010598T2
- Authority
- DE
- Germany
- Prior art keywords
- thick
- thermal conductivity
- high thermal
- film substrate
- metallic basis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/402,374 US5019675A (en) | 1989-09-05 | 1989-09-05 | Thick film substrate with highly thermally conductive metal base |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69010598D1 DE69010598D1 (de) | 1994-08-18 |
DE69010598T2 true DE69010598T2 (de) | 1995-01-19 |
Family
ID=23591619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69010598T Expired - Fee Related DE69010598T2 (de) | 1989-09-05 | 1990-09-05 | Dickschicht-Substrat auf metallischer Grundlage mit hoher thermischer Leitfähigkeit. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5019675A (de) |
EP (1) | EP0416898B1 (de) |
JP (1) | JPH03118161A (de) |
DE (1) | DE69010598T2 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5194877A (en) * | 1991-05-24 | 1993-03-16 | Hewlett-Packard Company | Process for manufacturing thermal ink jet printheads having metal substrates and printheads manufactured thereby |
US5901425A (en) | 1996-08-27 | 1999-05-11 | Topaz Technologies Inc. | Inkjet print head apparatus |
US6427597B1 (en) | 2000-01-27 | 2002-08-06 | Patrice M. Aurenty | Method of controlling image resolution on a substrate |
US8710523B2 (en) | 2006-08-11 | 2014-04-29 | E I Du Pont De Nemours And Company | Device chip carriers, modules, and methods of forming thereof |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3613230A (en) * | 1969-04-29 | 1971-10-19 | Bunker Ramo | Method of fabricating coaxial circuitry |
US4221925A (en) * | 1978-09-18 | 1980-09-09 | Western Electric Company, Incorporated | Printed circuit board |
JPS5635494A (en) * | 1979-08-30 | 1981-04-08 | Showa Denko Kk | High heat transfer electric insulating substrate |
GB2140460B (en) * | 1983-05-27 | 1986-06-25 | Dowty Electronics Ltd | Insulated metal substrates |
US4601777A (en) * | 1985-04-03 | 1986-07-22 | Xerox Corporation | Thermal ink jet printhead and process therefor |
DE3520945A1 (de) * | 1985-06-12 | 1986-12-18 | Anton Piller GmbH & Co KG, 3360 Osterode | Traegerelement zur aufnahme elektrischer und/oder elektronischer bauteile und/oder schaltungen |
US4786357A (en) * | 1987-11-27 | 1988-11-22 | Xerox Corporation | Thermal ink jet printhead and fabrication method therefor |
US4809428A (en) * | 1987-12-10 | 1989-03-07 | Hewlett-Packard Company | Thin film device for an ink jet printhead and process for the manufacturing same |
-
1989
- 1989-09-05 US US07/402,374 patent/US5019675A/en not_active Expired - Fee Related
-
1990
- 1990-08-30 JP JP2230443A patent/JPH03118161A/ja active Pending
- 1990-09-05 EP EP90309723A patent/EP0416898B1/de not_active Expired - Lifetime
- 1990-09-05 DE DE69010598T patent/DE69010598T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0416898A3 (en) | 1992-02-12 |
JPH03118161A (ja) | 1991-05-20 |
EP0416898A2 (de) | 1991-03-13 |
US5019675A (en) | 1991-05-28 |
EP0416898B1 (de) | 1994-07-13 |
DE69010598D1 (de) | 1994-08-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |