DE68927218D1 - Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor - Google Patents

Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor

Info

Publication number
DE68927218D1
DE68927218D1 DE68927218T DE68927218T DE68927218D1 DE 68927218 D1 DE68927218 D1 DE 68927218D1 DE 68927218 T DE68927218 T DE 68927218T DE 68927218 T DE68927218 T DE 68927218T DE 68927218 D1 DE68927218 D1 DE 68927218D1
Authority
DE
Germany
Prior art keywords
central processor
status code
status
code
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927218T
Other languages
English (en)
Other versions
DE68927218T2 (de
Inventor
Russell Gray Barbour
Carl A Soeder
Stephen J Ciavaglia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE68927218D1 publication Critical patent/DE68927218D1/de
Publication of DE68927218T2 publication Critical patent/DE68927218T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
DE68927218T 1988-10-18 1989-10-06 Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor Expired - Fee Related DE68927218T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25934588A 1988-10-18 1988-10-18

Publications (2)

Publication Number Publication Date
DE68927218D1 true DE68927218D1 (de) 1996-10-24
DE68927218T2 DE68927218T2 (de) 1997-02-06

Family

ID=22984558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927218T Expired - Fee Related DE68927218T2 (de) 1988-10-18 1989-10-06 Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor

Country Status (4)

Country Link
US (1) US5193157A (de)
EP (1) EP0365188B1 (de)
JP (1) JP3120152B2 (de)
DE (1) DE68927218T2 (de)

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JPH03288228A (ja) * 1990-04-04 1991-12-18 Koufu Nippon Denki Kk 情報処理装置
JP2580396B2 (ja) * 1991-01-31 1997-02-12 富士通株式会社 パイプラインにおける分岐命令制御方式
US5493687A (en) * 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
EP0550287A3 (en) * 1992-01-02 1994-08-17 Amdahl Corp Computer system having high performance processing for program status word (psw) key-setting instructions
JPH0576148U (ja) * 1992-03-13 1993-10-15 日本無線株式会社 携帯電話機用充電器
JP3730252B2 (ja) * 1992-03-31 2005-12-21 トランスメタ コーポレイション レジスタ名称変更方法及び名称変更システム
JP3637920B2 (ja) * 1992-05-01 2005-04-13 セイコーエプソン株式会社 スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
DE69320991T2 (de) * 1992-12-31 1999-01-28 Seiko Epson Corp System und verfahren zur änderung der namen von registern
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JPH06266556A (ja) * 1993-03-15 1994-09-22 Fujitsu Ltd データ処理装置
JP3452655B2 (ja) * 1993-09-27 2003-09-29 株式会社日立製作所 ディジタル信号処理プロセッサおよびそれを用いて命令を実行する方法
DE69430352T2 (de) * 1993-10-21 2003-01-30 Sun Microsystems Inc Gegenflusspipeline
EP0650116B1 (de) * 1993-10-21 1998-12-09 Sun Microsystems, Inc. Gegenflusspipelineprozessor
US5815695A (en) * 1993-10-28 1998-09-29 Apple Computer, Inc. Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor
WO1996025705A1 (en) * 1995-02-14 1996-08-22 Fujitsu Limited Structure and method for high-performance speculative execution processor providing special features
JPH08265405A (ja) * 1995-03-28 1996-10-11 Nec Corp コードレス電話機の充電端子構造
JPH0969047A (ja) 1995-09-01 1997-03-11 Sony Corp Ｒｉｓｃ型マイクロプロセッサおよび情報処理装置
US5761515A (en) * 1996-03-14 1998-06-02 International Business Machines Corporation Branch on cache hit/miss for compiler-assisted miss delay tolerance
US5881277A (en) * 1996-06-13 1999-03-09 Texas Instruments Incorporated Pipelined microprocessor with branch misprediction cache circuits, systems and methods
US5850553A (en) * 1996-11-12 1998-12-15 Hewlett-Packard Company Reducing the number of executed branch instructions in a code sequence
US6862563B1 (en) 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US7505974B2 (en) 1999-02-12 2009-03-17 Gropper Robert L Auto update utility for digital address books
US6883000B1 (en) 1999-02-12 2005-04-19 Robert L. Gropper Business card and contact management system
US6272618B1 (en) 1999-03-25 2001-08-07 Dell Usa, L.P. System and method for handling interrupts in a multi-processor computer
US6560754B1 (en) 1999-05-13 2003-05-06 Arc International Plc Method and apparatus for jump control in a pipelined processor
CN1167005C (zh) * 1999-05-13 2004-09-15 Arc国际美国控股公司 用于流水线化处理器中跳转控制的方法及装置
US6574728B1 (en) * 1999-08-10 2003-06-03 Cirrus Logic, Inc. Condition code stack architecture systems and methods
US6820193B1 (en) * 1999-12-17 2004-11-16 Koninklijke Philips Electronics N.V. Branch instructions with decoupled condition and address
WO2001069411A2 (en) 2000-03-10 2001-09-20 Arc International Plc Memory interface and method of interfacing between functional entities
US7114063B1 (en) * 2000-12-01 2006-09-26 Unisys Corporation Condition indicator for use by a conditional branch instruction
US7493470B1 (en) 2001-12-07 2009-02-17 Arc International, Plc Processor apparatus and methods optimized for control applications
US7299343B2 (en) * 2002-09-27 2007-11-20 Verisilicon Holdings (Cayman Islands) Co. Ltd. System and method for cooperative execution of multiple branching instructions in a processor
US9195460B1 (en) * 2006-05-02 2015-11-24 Nvidia Corporation Using condition codes in the presence of non-numeric values
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
US9952864B2 (en) * 2009-12-23 2018-04-24 Intel Corporation System, apparatus, and method for supporting condition codes
JP5866697B2 (ja) * 2012-02-23 2016-02-17 株式会社エルイーテック 複数のコンディションフラグを有するｃｐｕ
US9652242B2 (en) * 2012-05-02 2017-05-16 Apple Inc. Apparatus for predicate calculation in processor instruction set
US10713048B2 (en) * 2017-01-19 2020-07-14 International Business Machines Corporation Conditional branch to an indirectly specified location

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US4378589A (en) * 1976-12-27 1983-03-29 International Business Machines Corporation Undirectional looped bus microcomputer architecture
US4484303A (en) * 1979-06-19 1984-11-20 Gould Inc. Programmable controller
JPS6015745A (ja) * 1983-07-06 1985-01-26 Nec Corp 情報処理装置
US4578750A (en) * 1983-08-24 1986-03-25 Amdahl Corporation Code determination using half-adder based operand comparator
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
US5027315A (en) * 1984-09-28 1991-06-25 Advanced Micro Devices, Inc. Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions
US4791551A (en) * 1985-02-11 1988-12-13 Analog Devices, Inc. Microprogrammable devices using transparent latch
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
US4933897A (en) * 1986-02-07 1990-06-12 Advanced Micro Devices, Inc. Method for designing a control sequencer
US4845659A (en) * 1986-08-15 1989-07-04 International Business Machines Corporation Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations
US4811211A (en) * 1986-09-26 1989-03-07 Performance Semiconductor Corporation On-line overflow response system and ALU branching structure
US4967351A (en) * 1986-10-17 1990-10-30 Amdahl Corporation Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination
US4914581A (en) * 1987-10-26 1990-04-03 Motorola, Inc. Method and apparatus for explicitly evaluating conditions in a data processor
US4881194A (en) * 1987-11-16 1989-11-14 Intel Corporation Stored-program controller for equalizing conditional branch delays
EP0365187A3 (de) * 1988-10-18 1992-04-29 Apollo Computer Inc. Vorrichtung zur selektiven Ausführung von einem Verzweigungsbefehl folgenden Befehlen

Also Published As

Publication number Publication date
JP3120152B2 (ja) 2000-12-25
US5193157A (en) 1993-03-09
DE68927218T2 (de) 1997-02-06
EP0365188A3 (de) 1992-04-29
JPH02224025A (ja) 1990-09-06
EP0365188B1 (de) 1996-09-18
EP0365188A2 (de) 1990-04-25

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee