DE68917614D1 - Verfahren zum Ausrichten und zur Herstellung eines Verbindungszapfens. - Google Patents

Verfahren zum Ausrichten und zur Herstellung eines Verbindungszapfens.

Info

Publication number
DE68917614D1
DE68917614D1 DE68917614T DE68917614T DE68917614D1 DE 68917614 D1 DE68917614 D1 DE 68917614D1 DE 68917614 T DE68917614 T DE 68917614T DE 68917614 T DE68917614 T DE 68917614T DE 68917614 D1 DE68917614 D1 DE 68917614D1
Authority
DE
Germany
Prior art keywords
spigot
aligning
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68917614T
Other languages
English (en)
Other versions
DE68917614T2 (de
Inventor
Jeffrey E Brighton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE68917614D1 publication Critical patent/DE68917614D1/de
Application granted granted Critical
Publication of DE68917614T2 publication Critical patent/DE68917614T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE68917614T 1988-02-26 1989-01-26 Verfahren zum Ausrichten und zur Herstellung eines Verbindungszapfens. Expired - Fee Related DE68917614T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/161,573 US5025303A (en) 1988-02-26 1988-02-26 Product of pillar alignment and formation process

Publications (2)

Publication Number Publication Date
DE68917614D1 true DE68917614D1 (de) 1994-09-29
DE68917614T2 DE68917614T2 (de) 1994-12-22

Family

ID=22581752

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68917614T Expired - Fee Related DE68917614T2 (de) 1988-02-26 1989-01-26 Verfahren zum Ausrichten und zur Herstellung eines Verbindungszapfens.

Country Status (4)

Country Link
US (2) US5025303A (de)
EP (1) EP0329969B1 (de)
JP (1) JPH027544A (de)
DE (1) DE68917614T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2773366B2 (ja) * 1990-03-19 1998-07-09 富士通株式会社 多層配線基板の形成方法
JP3238395B2 (ja) * 1990-09-28 2001-12-10 株式会社東芝 半導体集積回路
JP3063338B2 (ja) * 1991-11-30 2000-07-12 日本電気株式会社 半導体装置およびその製造方法
IT1252539B (it) * 1991-12-18 1995-06-19 St Microelectronics Srl Procedimento per la realizzazione di strutture metrologiche particolarmente per la misura diretta di errori introdotti da sistemi di allineamento.
US5504375A (en) * 1992-03-02 1996-04-02 International Business Machines Corporation Asymmetric studs and connecting lines to minimize stress
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
JPH06314687A (ja) * 1993-04-30 1994-11-08 Sony Corp 多層配線構造の半導体装置およびその製造方法
KR970007174B1 (ko) * 1994-07-07 1997-05-03 현대전자산업 주식회사 반도체 소자의 금속배선 형성방법
KR960006068A (ko) * 1994-07-29 1996-02-23 가네꼬 히사시 반도체 장치 및 이의 제조 방법
US5650881A (en) * 1994-11-02 1997-07-22 Texas Instruments Incorporated Support post architecture for micromechanical devices
KR0167889B1 (ko) * 1995-06-09 1999-02-01 김주용 반도체 소자의 비아홀의 형성방법
US5700739A (en) * 1995-08-03 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Method of multi-step reactive ion etch for patterning adjoining semiconductor metallization layers
US5693568A (en) * 1995-12-14 1997-12-02 Advanced Micro Devices, Inc. Reverse damascene via structures
US5693556A (en) * 1995-12-29 1997-12-02 Cypress Semiconductor Corp. Method of making an antifuse metal post structure
US5639692A (en) * 1996-04-08 1997-06-17 Chartered Semiconductor Manufacturing Pte, Ltd. Non-etch back SOG process using a metal via stud
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
JPH10261709A (ja) * 1996-09-27 1998-09-29 Nec Corp 半導体装置の製造方法
US6291891B1 (en) 1998-01-13 2001-09-18 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device
TW425666B (en) * 1999-08-12 2001-03-11 Taiwan Semiconductor Mfg Manufacturing method for borderless via on semiconductor device
US6783999B1 (en) * 2003-06-20 2004-08-31 Infineon Technologies Ag Subtractive stud formation for MRAM manufacturing
EP2081224A1 (de) * 2007-12-27 2009-07-22 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Maskenloses Verfahren zur Vorbereitung von Metallkontakten für die Verbindung von Halbleitersubstraten
WO2018063324A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Chip assemblies employing solder bonds to back-side lands including an electrolytic nickel layer
US11508617B2 (en) * 2019-10-24 2022-11-22 Applied Materials, Inc. Method of forming interconnect for semiconductor device
US11257677B2 (en) 2020-01-24 2022-02-22 Applied Materials, Inc. Methods and devices for subtractive self-alignment

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
JPS57120295A (en) * 1981-01-17 1982-07-27 Mitsubishi Electric Corp Semiconductor memory device
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
JPS60136337A (ja) * 1983-12-22 1985-07-19 モノリシツク・メモリ−ズ・インコ−ポレイテツド ２重層処理においてヒロツク抑制層を形成する方法及びその構造物
JPS6164166A (ja) * 1984-09-06 1986-04-02 Toshiba Corp 半導体装置
US4674174A (en) * 1984-10-17 1987-06-23 Kabushiki Kaisha Toshiba Method for forming a conductor pattern using lift-off
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
US4851895A (en) * 1985-05-06 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Metallization for integrated devices
JPS6297353A (ja) * 1985-08-06 1987-05-06 テキサス　インスツルメンツ　インコ−ポレイテツド Ｖｌｓｉデバイス用の平面状金属相互接続
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
DE3627417A1 (de) * 1986-08-13 1988-02-18 Siemens Ag Verfahren zum herstellen von niederohmigen verbindungen in der isolationsschicht zwischen zwei metallisierungsebenen
JPH0770527B2 (ja) * 1987-02-27 1995-07-31 アメリカン テレフォン アンド テレグラフ カムパニー デバイス作製方法
ATE86797T1 (de) * 1988-12-16 1993-03-15 Siemens Ag Verfahren zur selbstjustierten herstellung von kontakten zwischen in uebereinander angeordneten verdrahtungsebenen einer integrierten schaltung enthaltenen leiterbahnen.

Also Published As

Publication number Publication date
US5025303A (en) 1991-06-18
US5436199A (en) 1995-07-25
EP0329969B1 (de) 1994-08-24
EP0329969A1 (de) 1989-08-30
DE68917614T2 (de) 1994-12-22
JPH027544A (ja) 1990-01-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee