DE68911174D1 - Methode zur Erzeugung von Ortsverbindungen mit Gebrauch von chlorenthaltenden Mitteln. - Google Patents

Methode zur Erzeugung von Ortsverbindungen mit Gebrauch von chlorenthaltenden Mitteln.

Info

Publication number
DE68911174D1
DE68911174D1 DE89101903T DE68911174T DE68911174D1 DE 68911174 D1 DE68911174 D1 DE 68911174D1 DE 89101903 T DE89101903 T DE 89101903T DE 68911174 T DE68911174 T DE 68911174T DE 68911174 D1 DE68911174 D1 DE 68911174D1
Authority
DE
Germany
Prior art keywords
chlorine
containing agents
generating local
local connections
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89101903T
Other languages
English (en)
Other versions
DE68911174T2 (de
Inventor
Monte A Douglas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE68911174D1 publication Critical patent/DE68911174D1/de
Application granted granted Critical
Publication of DE68911174T2 publication Critical patent/DE68911174T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
DE68911174T 1988-02-22 1989-02-03 Methode zur Erzeugung von Ortsverbindungen mit Gebrauch von chlorenthaltenden Mitteln. Expired - Fee Related DE68911174T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07159852 US4793896C1 (en) 1988-02-22 1988-02-22 Method for forming local interconnects using chlorine bearing agents

Publications (2)

Publication Number Publication Date
DE68911174D1 true DE68911174D1 (de) 1994-01-20
DE68911174T2 DE68911174T2 (de) 1994-06-16

Family

ID=22574356

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68911174T Expired - Fee Related DE68911174T2 (de) 1988-02-22 1989-02-03 Methode zur Erzeugung von Ortsverbindungen mit Gebrauch von chlorenthaltenden Mitteln.

Country Status (5)

Country Link
US (2) US4793896C1 (de)
EP (1) EP0332833B1 (de)
JP (1) JPH01289252A (de)
KR (1) KR890013724A (de)
DE (1) DE68911174T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4793896C1 (en) * 1988-02-22 2001-10-23 Texas Instruments Inc Method for forming local interconnects using chlorine bearing agents
US4957590A (en) * 1988-02-22 1990-09-18 Texas Instruments Incorporated Method for forming local interconnects using selective anisotropy
US5057186A (en) * 1989-07-28 1991-10-15 At&T Bell Laboratories Method of taper-etching with photoresist adhesion layer
US4980020A (en) * 1989-12-22 1990-12-25 Texas Instruments Incorporated Local interconnect etch technique
DE4117005C2 (de) * 1990-06-11 2003-07-24 Tokyo Electron Ltd Verfahren und Anordnung zum Einwirken mit einem Lichtstrahl in einen Entladungsraum
US5122225A (en) * 1990-11-21 1992-06-16 Texas Instruments Incorporated Selective etch method
JP3240724B2 (ja) * 1993-02-09 2001-12-25 ソニー株式会社 配線形成方法
US5420071A (en) * 1993-06-30 1995-05-30 Burke; Edmund Methods of forming local interconnections in semiconductor devices
JP3256048B2 (ja) * 1993-09-20 2002-02-12 富士通株式会社 半導体装置及びその製造方法
US5468296A (en) * 1993-12-17 1995-11-21 Lsi Logic Corporation Apparatus for igniting low pressure inductively coupled plasma
US5399237A (en) * 1994-01-27 1995-03-21 Applied Materials, Inc. Etching titanium nitride using carbon-fluoride and carbon-oxide gas
JP3238820B2 (ja) * 1994-02-18 2001-12-17 富士通株式会社 半導体装置
JPH07263544A (ja) * 1994-03-17 1995-10-13 Fujitsu Ltd 半導体装置及びその製造方法
US5696428A (en) * 1995-06-07 1997-12-09 Lsi Logic Corporation Apparatus and method using optical energy for specifying and quantitatively controlling chemically-reactive components of semiconductor processing plasma etching gas
JPH098297A (ja) * 1995-06-26 1997-01-10 Mitsubishi Electric Corp 半導体装置、その製造方法及び電界効果トランジスタ
US5935877A (en) * 1995-09-01 1999-08-10 Applied Materials, Inc. Etch process for forming contacts over titanium silicide
US5681486A (en) * 1996-02-23 1997-10-28 The Boeing Company Plasma descaling of titanium and titanium alloys
US5930639A (en) * 1996-04-08 1999-07-27 Micron Technology, Inc. Method for precision etching of platinum electrodes
US5750438A (en) * 1996-06-04 1998-05-12 United Microelectronics Corporation Method for fabricating a local interconnection structure
JPH10189483A (ja) * 1996-12-26 1998-07-21 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP3567081B2 (ja) * 1997-05-30 2004-09-15 ルーセント テクノロジーズ インコーポレーテッド Ｓｒａｍデバイスおよびその製造方法
US6562724B1 (en) * 1997-06-09 2003-05-13 Texas Instruments Incorporated Self-aligned stack formation
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US6448655B1 (en) 1998-04-28 2002-09-10 International Business Machines Corporation Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation
US6100185A (en) * 1998-08-14 2000-08-08 Micron Technology, Inc. Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
US6365507B1 (en) 1999-03-01 2002-04-02 Micron Technology, Inc. Method of forming integrated circuitry
US6524951B2 (en) * 1999-03-01 2003-02-25 Micron Technology, Inc. Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon
US7077721B2 (en) 2000-02-17 2006-07-18 Applied Materials, Inc. Pad assembly for electrochemical mechanical processing
US7067416B2 (en) * 2001-08-29 2006-06-27 Micron Technology, Inc. Method of forming a conductive contact
US6743715B1 (en) * 2002-05-07 2004-06-01 Taiwan Semiconductor Manufacturing Company Dry clean process to improve device gate oxide integrity (GOI) and reliability
US6707117B1 (en) * 2002-10-31 2004-03-16 National Semiconductor Corporation Method of providing semiconductor interconnects using silicide exclusion
US7230292B2 (en) * 2003-08-05 2007-06-12 Micron Technology, Inc. Stud electrode and process for making same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574177A (en) * 1982-02-01 1986-03-04 Texas Instruments Incorporated Plasma etch method for TiO2
JPS59175726A (ja) * 1983-03-25 1984-10-04 Fujitsu Ltd 半導体装置の製造方法
US4657628A (en) * 1985-05-01 1987-04-14 Texas Instruments Incorporated Process for patterning local interconnects
US4676866A (en) * 1985-05-01 1987-06-30 Texas Instruments Incorporated Process to increase tin thickness
JPS62186535A (ja) * 1986-02-12 1987-08-14 Fujitsu Ltd ドライエツチング装置
US4675073A (en) * 1986-03-07 1987-06-23 Texas Instruments Incorporated Tin etch process
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
US4793896C1 (en) * 1988-02-22 2001-10-23 Texas Instruments Inc Method for forming local interconnects using chlorine bearing agents

Also Published As

Publication number Publication date
US4863559A (en) 1989-09-05
US4793896C1 (en) 2001-10-23
US4863559B1 (en) 2000-11-21
JPH01289252A (ja) 1989-11-21
KR890013724A (ko) 1989-09-25
EP0332833B1 (de) 1993-12-08
US4793896A (en) 1988-12-27
DE68911174T2 (de) 1994-06-16
EP0332833A1 (de) 1989-09-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee