DE68900573D1 - Verfahren zum einkapseln von integrierten schaltungen, insbesondere fuer chipkarten. - Google Patents

Verfahren zum einkapseln von integrierten schaltungen, insbesondere fuer chipkarten.

Info

Publication number
DE68900573D1
DE68900573D1 DE8989402443T DE68900573T DE68900573D1 DE 68900573 D1 DE68900573 D1 DE 68900573D1 DE 8989402443 T DE8989402443 T DE 8989402443T DE 68900573 T DE68900573 T DE 68900573T DE 68900573 D1 DE68900573 D1 DE 68900573D1
Authority
DE
Germany
Prior art keywords
integrated circuits
chip cards
encapsulating integrated
encapsulating
cards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8989402443T
Other languages
English (en)
Inventor
Francis Steffen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=9369989&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68900573(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE68900573D1 publication Critical patent/DE68900573D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
DE8989402443T 1988-09-14 1989-09-07 Verfahren zum einkapseln von integrierten schaltungen, insbesondere fuer chipkarten. Expired - Lifetime DE68900573D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8811998A FR2636453B1 (fr) 1988-09-14 1988-09-14 Procede d'encapsulation de circuits-integres notamment pour cartes a puces

Publications (1)

Publication Number Publication Date
DE68900573D1 true DE68900573D1 (de) 1992-01-30

Family

ID=9369989

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8989402443T Expired - Lifetime DE68900573D1 (de) 1988-09-14 1989-09-07 Verfahren zum einkapseln von integrierten schaltungen, insbesondere fuer chipkarten.

Country Status (4)

Country Link
EP (1) EP0359632B2 (de)
JP (1) JP2604340B2 (de)
DE (1) DE68900573D1 (de)
FR (1) FR2636453B1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2560895B2 (ja) * 1990-07-25 1996-12-04 三菱電機株式会社 Ｉｃカードの製造方法およびｉｃカード
EP0472768A1 (de) * 1990-08-30 1992-03-04 Siemens Aktiengesellschaft Verfahren zum Befestigen eines Chipmoduls auf einer Chipkarte
DE4126874C2 (de) * 1991-08-14 1997-05-22 Orga Kartensysteme Gmbh Datenträger mit integriertem Schaltkreis
FR2686996B1 (fr) * 1992-01-31 1996-02-02 Solaic Sa Procede de fabrication d'une carte a memoire comprenant un micromodule equipe d'un capot, et carte a memoire ainsi obtenue.
DE4336501A1 (de) * 1993-10-26 1995-04-27 Giesecke & Devrient Gmbh Verfahren zur Herstellung von Ausweiskarten mit elektronischen Modulen
DE4401588C2 (de) * 1994-01-20 2003-02-20 Gemplus Gmbh Verfahren zum Verkappen eines Chipkarten-Moduls und Chipkarten-Modul
DE69512137T2 (de) * 1994-06-15 2000-05-25 Rue Cartes Et Systemes Paris D Herstellungsverfahren und Montage für IC-Karte.
JPH0885285A (ja) 1994-07-21 1996-04-02 Hitachi Maxell Ltd セキュリティカード用基板の製造方法、およびセキュリティカード用基板
WO1999004367A1 (en) * 1997-07-18 1999-01-28 Dai Nippon Printing Co., Ltd. Ic module, ic card, sealing resin for ic module, and method for manufacturing ic module
DE19731737A1 (de) * 1997-07-23 1998-09-17 Siemens Ag Chipmodul für einen kartenförmigen Datenträger, entsprechender Kartenkörper sowie Verfahren zur Befestigung des Chipmoduls im Kartenkörper
DE19732915C1 (de) 1997-07-30 1998-12-10 Siemens Ag Verfahren zur Herstellung eines Chipmoduls
FR2774198B1 (fr) * 1998-01-27 2001-08-31 Solaic Sa Procede de fixation d'un module electronique dans une cavite d'un corps d'objet portable, notamment corps de carte, par ultrasons
FR2797977B1 (fr) * 1999-08-25 2004-09-24 Gemplus Card Int Procede de fabrication d'un dispositif electronique portable comportant une etape de surmoulage directement sur le film support
DE10109993A1 (de) * 2001-03-01 2002-09-05 Giesecke & Devrient Gmbh Verfahren zur Herstellung eines Moduls
FR2838850B1 (fr) * 2002-04-18 2005-08-05 Framatome Connectors Int Procede de conditionnement de microcircuits electroniques pour carte a puce et microcircuit electronique ainsi obtenu
JP4853760B2 (ja) * 2005-08-05 2012-01-11 大日本印刷株式会社 Ｉｃカード、ｉｃカードの製造方法、およびｉｃカードの製造装置
EP1785916B1 (de) * 2005-11-14 2009-08-19 Tyco Electronics France SAS Smartcard-Körper, Smartcard und Herstellungsverfahren
KR100984132B1 (ko) * 2007-11-12 2010-09-28 삼성에스디아이 주식회사 반도체 패키지 및 그 실장방법
EP2447886A1 (de) * 2010-10-07 2012-05-02 Gemalto SA Gesichertes elektronisches Modul, Vorrichtung mit gesichertem elektronischen Modul, und entsprechendes Herstellungsverfahren
GB2548637A (en) * 2016-03-24 2017-09-27 Zwipe As Method of manufacturing an electronic card

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579799B1 (fr) * 1985-03-28 1990-06-22 Flonic Sa Procede de fabrication de cartes a memoire electronique et cartes obtenues suivant ledit procede
FR2579798B1 (fr) * 1985-04-02 1990-09-28 Ebauchesfabrik Eta Ag Procede de fabrication de modules electroniques pour cartes a microcircuits et modules obtenus selon ce procede
US4996411A (en) * 1986-07-24 1991-02-26 Schlumberger Industries Method of manufacturing a card having electronic memory and a card obtained by performing said method

Also Published As

Publication number Publication date
FR2636453A1 (fr) 1990-03-16
EP0359632A1 (de) 1990-03-21
EP0359632B2 (de) 1997-11-26
FR2636453B1 (fr) 1992-01-17
EP0359632B1 (de) 1991-12-18
JP2604340B2 (ja) 1997-04-30
JPH02197139A (ja) 1990-08-03

Similar Documents

Publication Publication Date Title
DE68900573D1 (de) Verfahren zum einkapseln von integrierten schaltungen, insbesondere fuer chipkarten.
DE59004053D1 (de) Trägerelement mit wenigstens einem integrierten schaltkreis, insbesondere zum einbau in chip-karten.
DE3582556D1 (de) Verfahren zum herstellen von kontakten fuer integrierte schaltungen.
DE3770318D1 (de) Anisotrope elektrizitaetsleitende klebstoffzusammensetzung, verfahren zum verbinden von stromkreisen und die so erhaltenen stromkreise.
DE69015511D1 (de) Verfahren und Vorrichtung zum Verbinden von Halbleitersubstraten.
DE59006252D1 (de) Chipkartenleser.
DE69420917T2 (de) Verfahren, um gestapelte Halbleiterchips zusammenzuschalten und Bauelement
DE69813645D1 (de) Chipkarte, System zum Verarbeiten von Chipkarten und Verfahren zum Beglaubigen von Chipkarten
DE68914696D1 (de) Fehlertolerierende Chipkarte.
DE3861889D1 (de) Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen.
DE3577771D1 (de) Elektronisches bauteil, insbesondere fuer eine chip-induktivitaet.
DE69014998D1 (de) Lokalverbindungen für integrierte Schaltungen.
DE69009259T2 (de) Verfahren zum Zusammensetzen von Halbleiteranordnungen.
DE3881447D1 (de) Vorrichtung zum anschliessen von karten mit integrierten schaltungen.
DE68907451T2 (de) Ausgangstreiberschaltung für Halbleiter-IC.
DE69406079D1 (de) Verfahren zum elektronischen Bezahlen, insbesondere mittels einer Chipkarte
DE59006322D1 (de) Chipkartenleser.
DE68918301T2 (de) Passivierungsverfahren für eine integrierte Schaltung.
DE59101337D1 (de) Vorrichtung zum aufnehmen von karten mit integrierten schaltkreisen.
DE3878065T2 (de) Testanordnung und -verfahren fuer integrierte schaltungen, womit das bestimmen von oberflaechenschichteffekten moeglich wird.
DE3579066D1 (de) System fuer die pruefung funktioneller elektronischer schaltungen.
DE69021998D1 (de) Verfahren zur herstellung von komplementären, integrierten halbleiterschaltungen.
DE69905659T2 (de) Chipkarte, System zum Verarbeiten von Chipkarten, und Verfahren zum Verarbeiten von Chipkarten
DE59611413D1 (de) Verfahren zum Herstellen von Chipkarten
DE3775993D1 (de) Geraet zum bestrahlen von elektronischen schaltungen.

Legal Events

Date Code Title Description
8363 Opposition against the patent
8366 Restricted maintained after opposition proceedings
8339 Ceased/non-payment of the annual fee