DE60334694D1 - On-chip Diagnose-Vefahren und -Block zur Speicherreparatur mit gemischter Redundanz ("IO" Redundanz und "Word-register" Redundanz) - Google Patents
On-chip Diagnose-Vefahren und -Block zur Speicherreparatur mit gemischter Redundanz ("IO" Redundanz und "Word-register" Redundanz)Info
- Publication number
- DE60334694D1 DE60334694D1 DE60334694T DE60334694T DE60334694D1 DE 60334694 D1 DE60334694 D1 DE 60334694D1 DE 60334694 T DE60334694 T DE 60334694T DE 60334694 T DE60334694 T DE 60334694T DE 60334694 D1 DE60334694 D1 DE 60334694D1
- Authority
- DE
- Germany
- Prior art keywords
- redundancy
- register
- word
- block
- mixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03292283A EP1517334B1 (de) | 2003-09-16 | 2003-09-16 | On-chip Diagnose-Vefahren und -Block zur Speicherreparatur mit gemischter Redundanz ("IO" Redundanz und "Word-register" Redundanz) |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60334694D1 true DE60334694D1 (de) | 2010-12-09 |
Family
ID=34178640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60334694T Expired - Lifetime DE60334694D1 (de) | 2003-09-16 | 2003-09-16 | On-chip Diagnose-Vefahren und -Block zur Speicherreparatur mit gemischter Redundanz ("IO" Redundanz und "Word-register" Redundanz) |
Country Status (3)
Country | Link |
---|---|
US (1) | US7386769B2 (de) |
EP (1) | EP1517334B1 (de) |
DE (1) | DE60334694D1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7275190B2 (en) * | 2004-11-08 | 2007-09-25 | Micron Technology, Inc. | Memory block quality identification in a memory device |
JP2007287272A (ja) * | 2006-04-19 | 2007-11-01 | Hitachi Ltd | 冗長線所要量算出システムおよびそれを用いた不良解析方法 |
US7768847B2 (en) | 2008-04-09 | 2010-08-03 | Rambus Inc. | Programmable memory repair scheme |
US10234507B2 (en) | 2016-07-20 | 2019-03-19 | International Business Machines Corporation | Implementing register array (RA) repair using LBIST |
CN113435652B (zh) * | 2021-07-01 | 2023-01-24 | 贵州电网有限责任公司 | 一种一次设备缺陷诊断与预测方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4460999A (en) * | 1981-07-15 | 1984-07-17 | Pacific Western Systems, Inc. | Memory tester having memory repair analysis under pattern generator control |
US4751656A (en) * | 1986-03-10 | 1988-06-14 | International Business Machines Corporation | Method for choosing replacement lines in a two dimensionally redundant array |
JP2842923B2 (ja) * | 1990-03-19 | 1999-01-06 | 株式会社アドバンテスト | 半導体メモリ試験装置 |
US6026505A (en) * | 1991-10-16 | 2000-02-15 | International Business Machines Corporation | Method and apparatus for real time two dimensional redundancy allocation |
JP3301047B2 (ja) * | 1993-09-16 | 2002-07-15 | 株式会社日立製作所 | 半導体メモリシステム |
JPH09306198A (ja) * | 1996-02-07 | 1997-11-28 | Lsi Logic Corp | 冗長列及び入/出力線を備えたasicメモリを修復するための方法 |
US6032264A (en) * | 1997-04-22 | 2000-02-29 | Micron Technology, Inc. | Apparatus and method implementing repairs on a memory device |
US5910921A (en) * | 1997-04-22 | 1999-06-08 | Micron Technology, Inc. | Self-test of a memory device |
JP2000195295A (ja) * | 1998-12-24 | 2000-07-14 | Advantest Corp | メモリデバイス試験装置 |
US6141267A (en) * | 1999-02-03 | 2000-10-31 | International Business Machines Corporation | Defect management engine for semiconductor memories and memory systems |
JP2000235800A (ja) * | 1999-02-12 | 2000-08-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6304989B1 (en) * | 1999-07-21 | 2001-10-16 | Credence Systems Corporation | Built-in spare row and column replacement analysis system for embedded memories |
JP4230061B2 (ja) * | 1999-07-21 | 2009-02-25 | 株式会社アドバンテスト | 不良救済解析器を搭載したメモリ試験装置 |
US20020108073A1 (en) * | 2001-02-02 | 2002-08-08 | Hughes Brian William | System for and method of operating a programmable column fail counter for redundancy allocation |
US7003704B2 (en) * | 2002-11-12 | 2006-02-21 | International Business Machines Corporation | Two-dimensional redundancy calculation |
EP1465204A3 (de) | 2003-02-12 | 2005-03-30 | Infineon Technologies AG | Verfahren und MBISR (Memory Built-In Self Repair) zum reparieren eines Speichers |
US7188274B2 (en) * | 2003-02-14 | 2007-03-06 | Logicvision, Inc. | Memory repair analysis method and circuit |
US6928377B2 (en) * | 2003-09-09 | 2005-08-09 | International Business Machines Corporation | Self-test architecture to implement data column redundancy in a RAM |
-
2003
- 2003-09-16 EP EP03292283A patent/EP1517334B1/de not_active Expired - Fee Related
- 2003-09-16 DE DE60334694T patent/DE60334694D1/de not_active Expired - Lifetime
-
2004
- 2004-09-16 US US10/942,274 patent/US7386769B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050091563A1 (en) | 2005-04-28 |
US7386769B2 (en) | 2008-06-10 |
EP1517334A1 (de) | 2005-03-23 |
EP1517334B1 (de) | 2010-10-27 |
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