DE60329993D1 - Speicherherstellungsverfahren mit bitleitungsisolation - Google Patents

Speicherherstellungsverfahren mit bitleitungsisolation

Info

Publication number
DE60329993D1
DE60329993D1 DE60329993T DE60329993T DE60329993D1 DE 60329993 D1 DE60329993 D1 DE 60329993D1 DE 60329993 T DE60329993 T DE 60329993T DE 60329993 T DE60329993 T DE 60329993T DE 60329993 D1 DE60329993 D1 DE 60329993D1
Authority
DE
Germany
Prior art keywords
manufacturing process
memory manufacturing
lead insulation
bit lead
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60329993T
Other languages
English (en)
Inventor
Mark T Ramsbey
Tazrien Kamal
Jean Y Yang
Emmanuil Lingunis
Hidehiko Shiraiwa
Yu Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Application granted granted Critical
Publication of DE60329993D1 publication Critical patent/DE60329993D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
DE60329993T 2002-04-08 2003-02-14 Speicherherstellungsverfahren mit bitleitungsisolation Expired - Lifetime DE60329993D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/118,732 US8673716B2 (en) 2002-04-08 2002-04-08 Memory manufacturing process with bitline isolation
PCT/US2003/004461 WO2003088353A1 (en) 2002-04-08 2003-02-14 Memory manufacturing process with bitline isolation

Publications (1)

Publication Number Publication Date
DE60329993D1 true DE60329993D1 (de) 2009-12-24

Family

ID=28674480

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60329993T Expired - Lifetime DE60329993D1 (de) 2002-04-08 2003-02-14 Speicherherstellungsverfahren mit bitleitungsisolation

Country Status (9)

Country Link
US (1) US8673716B2 (de)
EP (1) EP1493185B1 (de)
JP (1) JP2005522880A (de)
KR (1) KR20050003357A (de)
CN (1) CN1315180C (de)
AU (1) AU2003225570A1 (de)
DE (1) DE60329993D1 (de)
TW (1) TWI271822B (de)
WO (1) WO2003088353A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8673716B2 (en) 2002-04-08 2014-03-18 Spansion Llc Memory manufacturing process with bitline isolation

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720133B1 (en) * 2002-04-19 2004-04-13 Advanced Micro Devices, Inc. Memory manufacturing process using disposable ARC for wordline formation
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
CN101375390B (zh) * 2006-01-25 2013-06-05 日本电气株式会社 半导体器件及其制造方法
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US9111985B1 (en) * 2007-01-11 2015-08-18 Cypress Semiconductor Corporation Shallow bipolar junction transistor
JP2012023247A (ja) * 2010-07-15 2012-02-02 Panasonic Corp 半導体記憶装置及びその製造方法
TW201209595A (en) * 2010-08-26 2012-03-01 Walton Advanced Eng Inc Storage device with data sharing function
CN105304489B (zh) * 2014-07-01 2018-06-01 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
DE2947350A1 (de) * 1979-11-23 1981-05-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie
US4516313A (en) * 1983-05-27 1985-05-14 Ncr Corporation Unified CMOS/SNOS semiconductor fabrication process
US4640844A (en) 1984-03-22 1987-02-03 Siemens Aktiengesellschaft Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon
US5815433A (en) * 1994-12-27 1998-09-29 Nkk Corporation Mask ROM device with gate insulation film based in pad oxide film and/or nitride film
EP1039533A3 (de) * 1999-03-22 2001-04-04 Infineon Technologies North America Corp. Hochleistungs-DRAM und dessen Herstellungsverfahren
US6436759B1 (en) * 2001-01-19 2002-08-20 Microelectronics Corp. Method for fabricating a MOS transistor of an embedded memory
US6468838B2 (en) * 2001-03-01 2002-10-22 United Microelectronic Corp. Method for fabricating a MOS transistor of an embedded memory
US6566194B1 (en) * 2001-10-01 2003-05-20 Advanced Micro Devices, Inc. Salicided gate for virtual ground arrays
US8673716B2 (en) 2002-04-08 2014-03-18 Spansion Llc Memory manufacturing process with bitline isolation
US6797565B1 (en) * 2002-09-16 2004-09-28 Advanced Micro Devices, Inc. Methods for fabricating and planarizing dual poly scalable SONOS flash memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8673716B2 (en) 2002-04-08 2014-03-18 Spansion Llc Memory manufacturing process with bitline isolation

Also Published As

Publication number Publication date
WO2003088353A1 (en) 2003-10-23
TW200400601A (en) 2004-01-01
CN1315180C (zh) 2007-05-09
AU2003225570A8 (en) 2003-10-27
KR20050003357A (ko) 2005-01-10
EP1493185A1 (de) 2005-01-05
JP2005522880A (ja) 2005-07-28
US8673716B2 (en) 2014-03-18
US20030190786A1 (en) 2003-10-09
CN1647265A (zh) 2005-07-27
AU2003225570A1 (en) 2003-10-27
EP1493185B1 (de) 2009-11-11
TWI271822B (en) 2007-01-21

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Legal Events

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