DE60323847D1 - Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen - Google Patents

Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen

Info

Publication number
DE60323847D1
DE60323847D1 DE60323847T DE60323847T DE60323847D1 DE 60323847 D1 DE60323847 D1 DE 60323847D1 DE 60323847 T DE60323847 T DE 60323847T DE 60323847 T DE60323847 T DE 60323847T DE 60323847 D1 DE60323847 D1 DE 60323847D1
Authority
DE
Germany
Prior art keywords
stripes
stripe
virtual
physical
processing elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60323847T
Other languages
English (en)
Inventor
Herman Schmit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Carnegie Mellon University
Original Assignee
Carnegie Mellon University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Carnegie Mellon University filed Critical Carnegie Mellon University
Application granted granted Critical
Publication of DE60323847D1 publication Critical patent/DE60323847D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Storage Device Security (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
DE60323847T 2002-08-16 2003-08-14 Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen Expired - Fee Related DE60323847D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/222,645 US7263602B2 (en) 2002-08-16 2002-08-16 Programmable pipeline fabric utilizing partially global configuration buses
PCT/US2003/025391 WO2004017223A2 (en) 2002-08-16 2003-08-14 Programmable pipeline fabric utilizing partially global configuration buses

Publications (1)

Publication Number Publication Date
DE60323847D1 true DE60323847D1 (de) 2008-11-13

Family

ID=31715027

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60323847T Expired - Fee Related DE60323847D1 (de) 2002-08-16 2003-08-14 Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen

Country Status (8)

Country Link
US (1) US7263602B2 (de)
EP (1) EP1535189B1 (de)
JP (1) JP2005539293A (de)
CN (1) CN100392635C (de)
AT (1) ATE409916T1 (de)
AU (1) AU2003262645A1 (de)
DE (1) DE60323847D1 (de)
WO (1) WO2004017223A2 (de)

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JP4547198B2 (ja) * 2004-06-30 2010-09-22 富士通株式会社 演算装置、演算装置の制御方法、プログラム及びコンピュータ読取り可能記録媒体
JP4546775B2 (ja) * 2004-06-30 2010-09-15 富士通株式会社 時分割多重処理可能なリコンフィギュラブル回路
KR100662873B1 (ko) * 2006-01-03 2007-01-02 삼성전자주식회사 루프가속기 및 이를 포함하는 데이터 처리 시스템
US20110264892A1 (en) * 2008-10-14 2011-10-27 National University Corporation NARA Institute of Science and Technology Data processing device
JP5552855B2 (ja) * 2010-03-19 2014-07-16 富士ゼロックス株式会社 画像処理装置、画像形成システム及び画像処理プログラム
GB2535547B (en) * 2015-04-21 2017-01-11 Adaptive Array Systems Ltd Data processor
US11093251B2 (en) 2017-10-31 2021-08-17 Micron Technology, Inc. System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
WO2019191742A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric
US11048656B2 (en) 2018-03-31 2021-06-29 Micron Technology, Inc. Multi-threaded, self-scheduling reconfigurable computing fabric
WO2019191738A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric
WO2019191739A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric
EP3776238A1 (de) 2018-03-31 2021-02-17 Micron Technology, Inc. Ausführungssteuerung für eine selbstplanende rekonfigurierbare multithread-rechenmatrix
WO2019191740A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Multiple types of thread identifiers for a multi-threaded, self-scheduling reconfigurable computing fabric
CN111919203A (zh) 2018-03-31 2020-11-10 美光科技公司 使用重入队列的多线程自调度可重新配置计算架构的循环执行控制
WO2019191743A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Conditional branching control for a multi-threaded, self- scheduling reconfigurable computing fabric
US11573834B2 (en) 2019-08-22 2023-02-07 Micron Technology, Inc. Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
US11150900B2 (en) 2019-08-28 2021-10-19 Micron Technology, Inc. Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric
US11494331B2 (en) 2019-09-10 2022-11-08 Cornami, Inc. Reconfigurable processor circuit architecture
CN116521134A (zh) * 2023-03-13 2023-08-01 广州嘉为科技有限公司 在ci流水线执行过程中修改其参数的方法、装置及介质

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US5684980A (en) * 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
JP3308770B2 (ja) * 1994-07-22 2002-07-29 三菱電機株式会社 情報処理装置および情報処理装置における計算方法
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
JPH09106389A (ja) * 1995-10-12 1997-04-22 Sony Corp 信号処理装置
FI971718A (fi) * 1997-04-22 1998-10-23 Nokia Telecommunications Oy Korttipaikkojen lisääminen suurikapasiteettiseen väylään
US6167502A (en) * 1997-10-10 2000-12-26 Billions Of Operations Per Second, Inc. Method and apparatus for manifold array processing
JPH11259436A (ja) * 1998-03-10 1999-09-24 Toppan Printing Co Ltd データ並列処理方法
US6119215A (en) * 1998-06-29 2000-09-12 Cisco Technology, Inc. Synchronization and control system for an arrayed processing engine
US6442732B1 (en) * 1999-04-21 2002-08-27 Lucent Technologies, Inc. Virtual logic system for solving satisfiability problems using reconfigurable hardware
US6959378B2 (en) * 2000-11-06 2005-10-25 Broadcom Corporation Reconfigurable processing system and method
CN1156760C (zh) * 2000-12-12 2004-07-07 智原科技股份有限公司 适用于处理器的存储器数据存取装置及其存取方法
US6526559B2 (en) * 2001-04-13 2003-02-25 Interface & Control Systems, Inc. Method for creating circuit redundancy in programmable logic devices

Also Published As

Publication number Publication date
CN100392635C (zh) 2008-06-04
CN1688991A (zh) 2005-10-26
WO2004017223A2 (en) 2004-02-26
AU2003262645A8 (en) 2004-03-03
JP2005539293A (ja) 2005-12-22
AU2003262645A1 (en) 2004-03-03
EP1535189B1 (de) 2008-10-01
US20040034761A1 (en) 2004-02-19
WO2004017223A3 (en) 2004-04-08
ATE409916T1 (de) 2008-10-15
EP1535189A2 (de) 2005-06-01
US7263602B2 (en) 2007-08-28

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee