DE60320677D1 - Herstellungsverfahren von ausgerichteten strukturen auf beiden seiten einer dünnschicht - Google Patents
Herstellungsverfahren von ausgerichteten strukturen auf beiden seiten einer dünnschichtInfo
- Publication number
- DE60320677D1 DE60320677D1 DE60320677T DE60320677T DE60320677D1 DE 60320677 D1 DE60320677 D1 DE 60320677D1 DE 60320677 T DE60320677 T DE 60320677T DE 60320677 T DE60320677 T DE 60320677T DE 60320677 D1 DE60320677 D1 DE 60320677D1
- Authority
- DE
- Germany
- Prior art keywords
- mark
- sides
- thin layer
- pattern
- arranged structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000015572 biosynthetic process Effects 0.000 abstract 4
- 239000010410 layer Substances 0.000 abstract 4
- 239000012790 adhesive layer Substances 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000010409 thin film Substances 0.000 abstract 2
- 230000001629 suppression Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Thin Film Transistor (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0215980A FR2848725B1 (fr) | 2002-12-17 | 2002-12-17 | Procede de formation de motifs alignes de part et d'autre d'un film mince |
FR0215980 | 2002-12-17 | ||
PCT/FR2003/050179 WO2004057671A2 (fr) | 2002-12-17 | 2003-12-16 | Procede de formation de motifs alignes de part et d'autre d'un film mince |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60320677D1 true DE60320677D1 (de) | 2008-06-12 |
DE60320677T2 DE60320677T2 (de) | 2009-06-10 |
Family
ID=32338875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60320677T Expired - Lifetime DE60320677T2 (de) | 2002-12-17 | 2003-12-16 | Herstellungsverfahren von ausgerichteten strukturen auf beiden seiten einer dünnschicht |
Country Status (6)
Country | Link |
---|---|
US (1) | US7425509B2 (de) |
EP (1) | EP1573810B1 (de) |
AT (1) | ATE393965T1 (de) |
DE (1) | DE60320677T2 (de) |
FR (1) | FR2848725B1 (de) |
WO (1) | WO2004057671A2 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI248681B (en) * | 2004-03-29 | 2006-02-01 | Imec Inter Uni Micro Electr | Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel |
FR2925223B1 (fr) * | 2007-12-18 | 2010-02-19 | Soitec Silicon On Insulator | Procede d'assemblage avec marques enterrees |
FR2979481B1 (fr) | 2011-08-25 | 2016-07-01 | Commissariat Energie Atomique | Procede de realisation d'un circuit integre tridimensionnel |
FR3039699B1 (fr) | 2015-07-31 | 2017-07-28 | Commissariat Energie Atomique | Procede de realisation d'un dispositif electronique |
CN110494969B (zh) * | 2019-06-27 | 2020-08-25 | 长江存储科技有限责任公司 | 在形成三维存储器器件的阶梯结构中的标记图案 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
JP2777942B2 (ja) * | 1991-11-07 | 1998-07-23 | 富士通株式会社 | Mosトランジスタの製造方法 |
DE69232432T2 (de) * | 1991-11-20 | 2002-07-18 | Canon Kk | Verfahren zur Herstellung einer Halbleiteranordnung |
JPH05267663A (ja) * | 1992-03-17 | 1993-10-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH05308050A (ja) * | 1992-05-01 | 1993-11-19 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5436173A (en) * | 1993-01-04 | 1995-07-25 | Texas Instruments Incorporated | Method for forming a semiconductor on insulator device |
JPH1058738A (ja) * | 1996-08-19 | 1998-03-03 | Ricoh Co Ltd | 光書込装置 |
US5893744A (en) * | 1997-01-28 | 1999-04-13 | Advanced Micro Devices | Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench isolation |
US6184104B1 (en) * | 1998-09-10 | 2001-02-06 | Chartered Semiconductor Manufacturing Ltd. | Alignment mark strategy for oxide CMP |
US6300670B1 (en) * | 1999-07-26 | 2001-10-09 | Stmicroelectronics, Inc. | Backside bus vias |
US6261918B1 (en) * | 1999-10-04 | 2001-07-17 | Conexant Systems, Inc. | Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture |
JP3503888B2 (ja) * | 2000-09-01 | 2004-03-08 | 沖電気工業株式会社 | アライメントマーク及びその形成方法 |
US20050009298A1 (en) * | 2001-09-20 | 2005-01-13 | Shuichi Suzuki | Method for manufacturing semiconductor device |
US7220655B1 (en) * | 2001-12-17 | 2007-05-22 | Advanced Micro Devices, Inc. | Method of forming an alignment mark on a wafer, and a wafer comprising same |
-
2002
- 2002-12-17 FR FR0215980A patent/FR2848725B1/fr not_active Expired - Fee Related
-
2003
- 2003-12-16 AT AT03809991T patent/ATE393965T1/de not_active IP Right Cessation
- 2003-12-16 EP EP03809991A patent/EP1573810B1/de not_active Expired - Lifetime
- 2003-12-16 US US10/539,532 patent/US7425509B2/en active Active
- 2003-12-16 WO PCT/FR2003/050179 patent/WO2004057671A2/fr active IP Right Grant
- 2003-12-16 DE DE60320677T patent/DE60320677T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1573810B1 (de) | 2008-04-30 |
DE60320677T2 (de) | 2009-06-10 |
FR2848725A1 (fr) | 2004-06-18 |
WO2004057671A3 (fr) | 2004-10-21 |
ATE393965T1 (de) | 2008-05-15 |
US20060148256A1 (en) | 2006-07-06 |
EP1573810A2 (de) | 2005-09-14 |
US7425509B2 (en) | 2008-09-16 |
WO2004057671A2 (fr) | 2004-07-08 |
FR2848725B1 (fr) | 2005-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2007142788A3 (en) | Laser ablation resist | |
WO2003095358A3 (en) | Method of forming manofluidic channels | |
DE60323873D1 (de) | Ugehörige herstellungsmethode | |
DE69322970T2 (de) | Herstellung und benutzung einer siebdruckschablone mit erhöhten kanten | |
WO2008048928A3 (en) | Methods of patterning a material on polymeric substrates | |
ATE398343T1 (de) | Beschichtetes substrat mit frequenzselektiver oberfläche | |
ATE395147T1 (de) | Verfahren zum beschichten einer strukturierten trennlage | |
WO2008091279A3 (en) | Etching and hole arrays | |
ATE459986T1 (de) | Verfahren für die herstellung eigekapselten organischen elektronischen vorrichtungen | |
TW200518850A (en) | Method of coating | |
EP1039789A4 (de) | Verfahren zur herstellung einer mehrschichtigen gedruckten leiterplatte | |
DE60045239D1 (de) | Rastermikroskopspitzen benutzendes verfahren | |
BR0102061B1 (pt) | processo para a produÇço de uma camada revestida por pulverizaÇço tÉrmica graduada sobre um substrato. | |
WO2005114719A3 (en) | Method of forming a recessed structure employing a reverse tone process | |
TW200632542A (en) | Mask, mask forming method, pattern forming method, and wiring pattern forming method | |
ATE423336T1 (de) | Strukturierung von solid-state-merkmalen durch nanolithographisches direktschreibedrucken | |
DE60125484D1 (de) | Retroreflektierende folie mit gedruckter schicht | |
TW200629374A (en) | Patterning substrates employing multi-film layers defining etch-differential interfaces | |
TW429419B (en) | Method of manufacturing semiconductor devices | |
WO2003038956A1 (fr) | Procede de production d'un element emetteur de lumiere | |
DE60320677D1 (de) | Herstellungsverfahren von ausgerichteten strukturen auf beiden seiten einer dünnschicht | |
DE60325091D1 (de) | Flexible substrate mit einer beschichtung aus aktivkohle | |
BR0207882A (pt) | Formação de modelo metálico | |
DE60310537D1 (de) | Photomaske und verfahren zur photolithographischen mustererzeugung auf einem substrat unter benützung von hilfsstrukturen mit phasenänderung | |
ATE285583T1 (de) | Mikromechanisches herstellungsverfahren mit überblendeten masken |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |