DE60316702D1 - Mehrport-speicherzellen - Google Patents

Mehrport-speicherzellen

Info

Publication number
DE60316702D1
DE60316702D1 DE60316702T DE60316702T DE60316702D1 DE 60316702 D1 DE60316702 D1 DE 60316702D1 DE 60316702 T DE60316702 T DE 60316702T DE 60316702 T DE60316702 T DE 60316702T DE 60316702 D1 DE60316702 D1 DE 60316702D1
Authority
DE
Germany
Prior art keywords
memory cells
port memory
port
cells
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60316702T
Other languages
English (en)
Other versions
DE60316702T2 (de
Inventor
Raj Kumar Jain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60316702D1 publication Critical patent/DE60316702D1/de
Publication of DE60316702T2 publication Critical patent/DE60316702T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60316702T 2002-09-26 2003-08-29 Mehrport-speicherzellen Expired - Lifetime DE60316702T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US65212 1998-04-23
US10/065,212 US7333388B2 (en) 2001-10-03 2002-09-26 Multi-port memory cells
PCT/EP2003/009618 WO2004029981A2 (en) 2002-09-26 2003-08-29 Multi-port memory cells

Publications (2)

Publication Number Publication Date
DE60316702D1 true DE60316702D1 (de) 2007-11-15
DE60316702T2 DE60316702T2 (de) 2008-07-17

Family

ID=32041297

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60316702T Expired - Lifetime DE60316702T2 (de) 2002-09-26 2003-08-29 Mehrport-speicherzellen

Country Status (6)

Country Link
US (1) US7333388B2 (de)
EP (1) EP1543525B1 (de)
JP (1) JP4176719B2 (de)
CN (1) CN100454434C (de)
DE (1) DE60316702T2 (de)
WO (1) WO2004029981A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7617356B2 (en) * 2002-12-31 2009-11-10 Intel Corporation Refresh port for a dynamic memory
JP4439838B2 (ja) * 2003-05-26 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
KR100800384B1 (ko) 2006-06-20 2008-02-01 삼성전자주식회사 반도체 메모리 장치 및 이에 따른 셀프 리프레쉬 방법
CN101131858B (zh) * 2007-09-28 2011-03-23 山东大学 三维多端口存储器及其控制方法
SG10201700467UA (en) * 2010-02-07 2017-02-27 Zeno Semiconductor Inc Semiconductor memory device having electrically floating body transistor, and having both volatile and non-volatile functionality and method

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577293A (en) 1984-06-01 1986-03-18 International Business Machines Corporation Distributed, on-chip cache
JPS6111993A (ja) 1984-06-28 1986-01-20 Toshiba Corp 半導体記憶装置
JPS63144494A (ja) 1986-12-05 1988-06-16 Alps Electric Co Ltd メインメモリ−のリフレツシユ方式
JPH04257048A (ja) 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
EP0895162A3 (de) 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern
GB9208493D0 (en) * 1992-04-16 1992-06-03 Thomson Consumer Electronics Dual port video memory
JPH06337815A (ja) 1993-05-28 1994-12-06 Hitachi Ltd データ処理装置
JP3569310B2 (ja) * 1993-10-14 2004-09-22 株式会社ルネサステクノロジ 半導体記憶装置
JP3199207B2 (ja) 1993-12-16 2001-08-13 シャープ株式会社 マルチポート半導体記憶装置
US5822760A (en) * 1994-01-31 1998-10-13 Fujitsu Limited Cache-memory system having multidimensional cache
US5566318A (en) * 1994-08-02 1996-10-15 Ramtron International Corporation Circuit with a single address register that augments a memory controller by enabling cache reads and page-mode writes
AU3412295A (en) * 1994-09-01 1996-03-22 Gary L. Mcalpine A multi-port memory system including read and write buffer interfaces
US5657266A (en) * 1995-06-30 1997-08-12 Micron Technology, Inc. Single ended transfer circuit
US6131140A (en) * 1995-12-22 2000-10-10 Cypress Semiconductor Corp. Integrated cache memory with system control logic and adaptation of RAM bus to a cache pinout
US6223260B1 (en) * 1996-01-25 2001-04-24 Unisys Corporation Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
US5844856A (en) * 1996-06-19 1998-12-01 Cirrus Logic, Inc. Dual port memories and systems and methods using the same
US6256256B1 (en) * 1998-01-30 2001-07-03 Silicon Aquarius, Inc. Dual port random access memories and systems using the same
US6216205B1 (en) * 1998-05-21 2001-04-10 Integrated Device Technology, Inc. Methods of controlling memory buffers having tri-port cache arrays therein
DE59903684D1 (de) 1998-09-30 2003-01-16 Siemens Ag Dual-port speicherzelle
US5999474A (en) 1998-10-01 1999-12-07 Monolithic System Tech Inc Method and apparatus for complete hiding of the refresh of a semiconductor memory
US6546461B1 (en) * 2000-11-22 2003-04-08 Integrated Device Technology, Inc. Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein
US6594196B2 (en) * 2000-11-29 2003-07-15 International Business Machines Corporation Multi-port memory device and system for addressing the multi-port memory device

Also Published As

Publication number Publication date
DE60316702T2 (de) 2008-07-17
CN1675717A (zh) 2005-09-28
JP4176719B2 (ja) 2008-11-05
EP1543525B1 (de) 2007-10-03
US20030063515A1 (en) 2003-04-03
US7333388B2 (en) 2008-02-19
WO2004029981A3 (en) 2004-10-14
JP2005536004A (ja) 2005-11-24
WO2004029981A2 (en) 2004-04-08
EP1543525A2 (de) 2005-06-22
CN100454434C (zh) 2009-01-21

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Legal Events

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