DE60314530T2 - Verfahren und system zum debuggen unter verwendung duplizierter logik - Google Patents

Verfahren und system zum debuggen unter verwendung duplizierter logik Download PDF

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Publication number
DE60314530T2
DE60314530T2 DE60314530T DE60314530T DE60314530T2 DE 60314530 T2 DE60314530 T2 DE 60314530T2 DE 60314530 T DE60314530 T DE 60314530T DE 60314530 T DE60314530 T DE 60314530T DE 60314530 T2 DE60314530 T2 DE 60314530T2
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DE
Germany
Prior art keywords
circuit
logic
transfer level
register transfer
level netlist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314530T
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German (de)
English (en)
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DE60314530D1 (de
Inventor
Chun Kit Portland NG
Kenneth S. Los Altos MCELVAIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synplicity LLC
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Synplicity LLC
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Publication date
Application filed by Synplicity LLC filed Critical Synplicity LLC
Publication of DE60314530D1 publication Critical patent/DE60314530D1/de
Application granted granted Critical
Publication of DE60314530T2 publication Critical patent/DE60314530T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
DE60314530T 2002-08-09 2003-08-05 Verfahren und system zum debuggen unter verwendung duplizierter logik Expired - Lifetime DE60314530T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/215,869 US6904576B2 (en) 2002-08-09 2002-08-09 Method and system for debugging using replicated logic
US215869 2002-08-09
PCT/US2003/024601 WO2004015596A2 (en) 2002-08-09 2003-08-05 Method and system for debugging using replicated logic

Publications (2)

Publication Number Publication Date
DE60314530D1 DE60314530D1 (de) 2007-08-02
DE60314530T2 true DE60314530T2 (de) 2008-02-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314530T Expired - Lifetime DE60314530T2 (de) 2002-08-09 2003-08-05 Verfahren und system zum debuggen unter verwendung duplizierter logik

Country Status (7)

Country Link
US (2) US6904576B2 (enExample)
EP (1) EP1546947B1 (enExample)
JP (1) JP4806529B2 (enExample)
AT (1) ATE365349T1 (enExample)
AU (1) AU2003261401A1 (enExample)
DE (1) DE60314530T2 (enExample)
WO (1) WO2004015596A2 (enExample)

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US8756557B2 (en) * 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
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CN106886210B (zh) * 2017-01-04 2019-03-08 北京航天自动控制研究所 基于序列触发拍照的火工品时序测试装置
US10409994B1 (en) 2017-03-01 2019-09-10 National Technology & Engineering Solutions Of Sandia, Llc FPGA/ASIC framework and method for requirements-based trust assessment
CN110988662B (zh) * 2019-12-09 2022-08-02 上海国微思尔芯技术股份有限公司 一种基于fpga原型验证开发板的信号调试系统及方法
CN113095015B (zh) * 2021-05-08 2024-05-24 中国科学院上海微系统与信息技术研究所 Sfq时序电路综合计算方法、系统以及终端
CN113608491B (zh) * 2021-07-16 2022-09-02 广东财经大学 一种编译延时逻辑原理图到字节码方法
CN114254575A (zh) * 2021-12-10 2022-03-29 山东云海国创云计算装备产业创新中心有限公司 一种生成寄存器转换级文件列表文件的方法和装置
CN116108783B (zh) * 2023-04-04 2023-07-18 上海思尔芯技术股份有限公司 分块逻辑时序分析建模及处理方法、系统、设备及介质

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Also Published As

Publication number Publication date
DE60314530D1 (de) 2007-08-02
US6904576B2 (en) 2005-06-07
WO2004015596A3 (en) 2004-06-03
US20080270958A1 (en) 2008-10-30
US7962869B2 (en) 2011-06-14
WO2004015596A2 (en) 2004-02-19
ATE365349T1 (de) 2007-07-15
EP1546947B1 (en) 2007-06-20
AU2003261401A1 (en) 2004-02-25
US20040030999A1 (en) 2004-02-12
EP1546947A2 (en) 2005-06-29
JP4806529B2 (ja) 2011-11-02
JP2005535965A (ja) 2005-11-24

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