AU2003261401A1 - Method and system for debugging using replicated logic - Google Patents

Method and system for debugging using replicated logic

Info

Publication number
AU2003261401A1
AU2003261401A1 AU2003261401A AU2003261401A AU2003261401A1 AU 2003261401 A1 AU2003261401 A1 AU 2003261401A1 AU 2003261401 A AU2003261401 A AU 2003261401A AU 2003261401 A AU2003261401 A AU 2003261401A AU 2003261401 A1 AU2003261401 A1 AU 2003261401A1
Authority
AU
Australia
Prior art keywords
circuit
logic
replicated
trigger condition
replicated portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003261401A
Other languages
English (en)
Inventor
Kenneth S. Mcelvain
Chun Kit Ng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synplicity LLC
Original Assignee
Synplicity LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synplicity LLC filed Critical Synplicity LLC
Publication of AU2003261401A1 publication Critical patent/AU2003261401A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
AU2003261401A 2002-08-09 2003-08-05 Method and system for debugging using replicated logic Abandoned AU2003261401A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/215,869 US6904576B2 (en) 2002-08-09 2002-08-09 Method and system for debugging using replicated logic
US10/215,869 2002-08-09
PCT/US2003/024601 WO2004015596A2 (en) 2002-08-09 2003-08-05 Method and system for debugging using replicated logic

Publications (1)

Publication Number Publication Date
AU2003261401A1 true AU2003261401A1 (en) 2004-02-25

Family

ID=31494954

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003261401A Abandoned AU2003261401A1 (en) 2002-08-09 2003-08-05 Method and system for debugging using replicated logic

Country Status (7)

Country Link
US (2) US6904576B2 (enExample)
EP (1) EP1546947B1 (enExample)
JP (1) JP4806529B2 (enExample)
AT (1) ATE365349T1 (enExample)
AU (1) AU2003261401A1 (enExample)
DE (1) DE60314530T2 (enExample)
WO (1) WO2004015596A2 (enExample)

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US10409994B1 (en) 2017-03-01 2019-09-10 National Technology & Engineering Solutions Of Sandia, Llc FPGA/ASIC framework and method for requirements-based trust assessment
CN110988662B (zh) * 2019-12-09 2022-08-02 上海国微思尔芯技术股份有限公司 一种基于fpga原型验证开发板的信号调试系统及方法
CN113095015B (zh) * 2021-05-08 2024-05-24 中国科学院上海微系统与信息技术研究所 Sfq时序电路综合计算方法、系统以及终端
CN113608491B (zh) * 2021-07-16 2022-09-02 广东财经大学 一种编译延时逻辑原理图到字节码方法
CN114254575A (zh) * 2021-12-10 2022-03-29 山东云海国创云计算装备产业创新中心有限公司 一种生成寄存器转换级文件列表文件的方法和装置
CN116108783B (zh) * 2023-04-04 2023-07-18 上海思尔芯技术股份有限公司 分块逻辑时序分析建模及处理方法、系统、设备及介质

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Also Published As

Publication number Publication date
DE60314530D1 (de) 2007-08-02
US6904576B2 (en) 2005-06-07
WO2004015596A3 (en) 2004-06-03
US20080270958A1 (en) 2008-10-30
US7962869B2 (en) 2011-06-14
DE60314530T2 (de) 2008-02-14
WO2004015596A2 (en) 2004-02-19
ATE365349T1 (de) 2007-07-15
EP1546947B1 (en) 2007-06-20
US20040030999A1 (en) 2004-02-12
EP1546947A2 (en) 2005-06-29
JP4806529B2 (ja) 2011-11-02
JP2005535965A (ja) 2005-11-24

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Legal Events

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MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase