DE60224438D1 - Aggregation von hardwareereignissen in mehrfach knotensystemen - Google Patents

Aggregation von hardwareereignissen in mehrfach knotensystemen

Info

Publication number
DE60224438D1
DE60224438D1 DE60224438T DE60224438T DE60224438D1 DE 60224438 D1 DE60224438 D1 DE 60224438D1 DE 60224438 T DE60224438 T DE 60224438T DE 60224438 T DE60224438 T DE 60224438T DE 60224438 D1 DE60224438 D1 DE 60224438D1
Authority
DE
Germany
Prior art keywords
node
aggregation
hardware events
primary node
multiple node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60224438T
Other languages
English (en)
Other versions
DE60224438T2 (de
Inventor
Richard A Lary
Daniel H Bax
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE60224438D1 publication Critical patent/DE60224438D1/de
Publication of DE60224438T2 publication Critical patent/DE60224438T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Stored Programmes (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Power Sources (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Debugging And Monitoring (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE60224438T 2001-10-01 2002-09-26 Aggregation von hardwareereignissen in mehrfach knotensystemen Expired - Lifetime DE60224438T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US968768 2001-10-01
US09/968,768 US6988155B2 (en) 2001-10-01 2001-10-01 Aggregation of hardware events in multi-node systems
PCT/US2002/030967 WO2003029999A1 (en) 2001-10-01 2002-09-26 Aggregation of hardware events in multi-node systems

Publications (2)

Publication Number Publication Date
DE60224438D1 true DE60224438D1 (de) 2008-02-14
DE60224438T2 DE60224438T2 (de) 2009-01-22

Family

ID=25514747

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224438T Expired - Lifetime DE60224438T2 (de) 2001-10-01 2002-09-26 Aggregation von hardwareereignissen in mehrfach knotensystemen

Country Status (8)

Country Link
US (1) US6988155B2 (de)
EP (1) EP1449097B1 (de)
JP (1) JP3940397B2 (de)
CN (1) CN1303545C (de)
AT (1) ATE382898T1 (de)
DE (1) DE60224438T2 (de)
TW (1) TWI235920B (de)
WO (1) WO2003029999A1 (de)

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US6889277B2 (en) * 2002-04-18 2005-05-03 Sun Microsystems, Inc. System and method for dynamically tuning interrupt coalescing parameters
US6988156B2 (en) * 2002-04-18 2006-01-17 Sun Microsystems, Inc. System and method for dynamically tuning interrupt coalescing parameters
US7197587B2 (en) * 2002-06-19 2007-03-27 Hewlett-Packard Development Company, L.P. Systems-events core for monitorings system events for a cellular computer system within a parent computer system, system-event manager for monitoring system events for more than one cellular computer system, and related system and method
US7305508B2 (en) * 2003-10-22 2007-12-04 Hewlett-Packard Development Company, L.P. Semaphoring system between system firmware and hardware manipulation subsystem
US7254726B2 (en) * 2003-11-10 2007-08-07 Dell Products L.P. System and method for managing system events by creating virtual events in an information handling system
US7752371B2 (en) * 2003-12-29 2010-07-06 Broadcom Corporation System and method for interrupt abstraction
US7496929B2 (en) * 2004-05-28 2009-02-24 Intel Corporation Performance of operations on a hardware resource through integral interpretive execution
US20060047878A1 (en) * 2004-08-25 2006-03-02 Zilavy Daniel V GPE register block
US7389297B1 (en) * 2004-09-02 2008-06-17 Sun Microsystems, Inc. Method for exit negotiation with aggregate application descendents
US8745124B2 (en) * 2005-10-31 2014-06-03 Ca, Inc. Extensible power control for an autonomically controlled distributed computing system
JP4960066B2 (ja) * 2006-11-15 2012-06-27 株式会社東芝 情報処理装置、および情報処理装置の制御方法
US7949813B2 (en) * 2007-02-06 2011-05-24 Broadcom Corporation Method and system for processing status blocks in a CPU based on index values and interrupt mapping
CN102495792A (zh) * 2011-11-04 2012-06-13 杭州中天微系统有限公司 在线调试多事件控制和实时监视的接口装置
US9940272B1 (en) 2015-04-09 2018-04-10 Juniper Networks, Inc. Hardware-based handling of missing interrupt propagation
US9886332B2 (en) * 2015-05-04 2018-02-06 International Business Machines Corporation Storage and application intercommunication using ACPI
US9875167B1 (en) * 2017-03-29 2018-01-23 Google Inc. Distributed hardware tracing
US10365987B2 (en) 2017-03-29 2019-07-30 Google Llc Synchronous hardware event collection
TWI733284B (zh) * 2019-12-24 2021-07-11 瑞昱半導體股份有限公司 硬體設定裝置及其硬體設定方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5165018A (en) 1987-01-05 1992-11-17 Motorola, Inc. Self-configuration of nodes in a distributed message-based operating system
JPH0268632A (ja) * 1988-09-05 1990-03-08 Toshiba Corp 割込み制御装置
US5282272A (en) * 1990-12-21 1994-01-25 Intel Corporation Interrupt distribution scheme for a computer bus
US5282271A (en) * 1991-10-30 1994-01-25 I-Cube Design Systems, Inc. I/O buffering system to a programmable switching apparatus
JP3177117B2 (ja) 1994-05-11 2001-06-18 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 複数のノード内の制御コードを更新する方法および装置
JPH07311752A (ja) 1994-05-11 1995-11-28 Internatl Business Mach Corp <Ibm> 分散データ処理システム及び初期プログラムロード方法
US5842026A (en) * 1996-07-01 1998-11-24 Sun Microsystems, Inc. Interrupt transfer management process and system for a multi-processor environment
US5968189A (en) * 1997-04-08 1999-10-19 International Business Machines Corporation System of reporting errors by a hardware element of a distributed computer system
US6247091B1 (en) * 1997-04-28 2001-06-12 International Business Machines Corporation Method and system for communicating interrupts between nodes of a multinode computer system
US6055643A (en) 1997-09-25 2000-04-25 Compaq Computer Corp. System management method and apparatus for supporting non-dedicated event detection
US6256740B1 (en) 1998-02-06 2001-07-03 Ncr Corporation Name service for multinode system segmented into I/O and compute nodes, generating guid at I/O node and exporting guid to compute nodes via interconnect fabric
US6247077B1 (en) 1998-02-06 2001-06-12 Ncr Corporation Highly-scalable parallel processing computer system architecture
US6219742B1 (en) 1998-04-29 2001-04-17 Compaq Computer Corporation Method and apparatus for artificially generating general purpose events in an ACPI environment
US6148361A (en) * 1998-12-17 2000-11-14 International Business Machines Corporation Interrupt architecture for a non-uniform memory access (NUMA) data processing system
US6272618B1 (en) * 1999-03-25 2001-08-07 Dell Usa, L.P. System and method for handling interrupts in a multi-processor computer
US6457135B1 (en) 1999-08-10 2002-09-24 Intel Corporation System and method for managing a plurality of processor performance states
US6691234B1 (en) * 2000-06-16 2004-02-10 Intel Corporation Method and apparatus for executing instructions loaded into a reserved portion of system memory for transitioning a computer system from a first power state to a second power state

Also Published As

Publication number Publication date
DE60224438T2 (de) 2009-01-22
CN1561493A (zh) 2005-01-05
US6988155B2 (en) 2006-01-17
US20030065853A1 (en) 2003-04-03
CN1303545C (zh) 2007-03-07
EP1449097A1 (de) 2004-08-25
EP1449097B1 (de) 2008-01-02
WO2003029999A1 (en) 2003-04-10
JP2005505053A (ja) 2005-02-17
JP3940397B2 (ja) 2007-07-04
TWI235920B (en) 2005-07-11
EP1449097A4 (de) 2007-02-28
ATE382898T1 (de) 2008-01-15

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition