BR9907848A - Interrupções em computador sem baixo desempenho com comutação de tarefas - Google Patents

Interrupções em computador sem baixo desempenho com comutação de tarefas

Info

Publication number
BR9907848A
BR9907848A BR9907848-1A BR9907848A BR9907848A BR 9907848 A BR9907848 A BR 9907848A BR 9907848 A BR9907848 A BR 9907848A BR 9907848 A BR9907848 A BR 9907848A
Authority
BR
Brazil
Prior art keywords
task
tasks
term
auxiliary
interruptions
Prior art date
Application number
BR9907848-1A
Other languages
English (en)
Inventor
Brian Donovan
Original Assignee
Xyron Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xyron Corp filed Critical Xyron Corp
Publication of BR9907848A publication Critical patent/BR9907848A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Hardware Redundancy (AREA)

Abstract

"INTERRUPçõES EM COMPUTADOR SEM BAIXO DESEMPENHO COM COMUTAçãO DE TAREFAS". A invenção constitui um sistema de variação de tarefas e de interrupção sem baixo desempenho de hardware único, para a redução ou a eliminação de latência de interrupção, na medida em que o baixo processamento na variação de tarefas provoca retardos nas arquiteturas do computador. Sem perda de tempo, o sistema realiza o salvamento e a restauração completos do estado da tarefa entre um ciclo e o seguinte, sem intervenção de software. Para cada Unidade de Processamento Central(1), a invenção usa um ou mais serializadores de termos auxiliares (3, 4), em que um serializador de termos (4) é usado com o serializador de termos "em processamento" e um dos serializadores de termos auxiliares é fixado na memória de armazenamento de tarefas. A invenção alterna as conexões entre os registros "em processamento" e os registros auxiliares alternados, enquanto transfere outras tarefas para e da memória de armazenamento de tarefas (2). A invenção proporciona um sistema de ligação de tarefas para propiciar a ligação de tarefas, para execução sequencial obrigatória das tarefas ligadas. Além disso, a invenção inclui um sistema contador de "impaciência" de prioridade, para aumentar as prioridades relativas das várias tarefas, na medida em que se aproximam das suas datas limites das tarefas.
BR9907848-1A 1998-02-13 1999-02-05 Interrupções em computador sem baixo desempenho com comutação de tarefas BR9907848A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/023,333 US5987601A (en) 1997-02-14 1998-02-13 Zero overhead computer interrupts with task switching
PCT/US1999/002575 WO1999041661A1 (en) 1998-02-13 1999-02-05 Zero overhead computer interrupts with task switching

Publications (1)

Publication Number Publication Date
BR9907848A true BR9907848A (pt) 2002-05-07

Family

ID=21814484

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9907848-1A BR9907848A (pt) 1998-02-13 1999-02-05 Interrupções em computador sem baixo desempenho com comutação de tarefas

Country Status (14)

Country Link
US (2) US5987601A (pt)
EP (1) EP1062572A4 (pt)
JP (1) JP2002503845A (pt)
KR (3) KR100617357B1 (pt)
CN (1) CN1116639C (pt)
AU (1) AU2659899A (pt)
BR (1) BR9907848A (pt)
CA (1) CA2320913C (pt)
HK (1) HK1036663A1 (pt)
ID (1) ID26818A (pt)
MX (1) MXPA00007850A (pt)
NO (1) NO20004043L (pt)
TW (1) TW448366B (pt)
WO (1) WO1999041661A1 (pt)

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KR100852563B1 (ko) 2000-10-18 2008-08-18 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 디지털 신호 처리 장치 및 방법
US20030014474A1 (en) * 2001-05-30 2003-01-16 Mckaig Ray S. Alternate zero overhead task change circuit
US20040172631A1 (en) * 2001-06-20 2004-09-02 Howard James E Concurrent-multitasking processor
US7136419B2 (en) 2002-06-20 2006-11-14 Lightfleet Corporation Pulse width communications using precision timing
US6920632B2 (en) * 2002-08-23 2005-07-19 Xyron Corporation Dynamic multilevel task management method and apparatus
JP2005165961A (ja) * 2003-12-05 2005-06-23 Matsushita Electric Ind Co Ltd 動的再構成論理回路装置、割込制御方法、及び、半導体集積回路
US9286445B2 (en) * 2003-12-18 2016-03-15 Red Hat, Inc. Rights management system
US8533716B2 (en) * 2004-03-31 2013-09-10 Synopsys, Inc. Resource management in a multicore architecture
US7779239B2 (en) * 2004-07-28 2010-08-17 Intel Corporation User opt-in processor feature control capability
US9038070B2 (en) 2004-09-14 2015-05-19 Synopsys, Inc. Debug in a multicore architecture
US7149129B2 (en) * 2004-10-25 2006-12-12 Lattice Semiconductor Corporation Memory output data systems and methods with feedback
JP4529661B2 (ja) * 2004-12-02 2010-08-25 株式会社アドヴィックス Ａｂｓ制御装置
US7224622B2 (en) * 2005-02-14 2007-05-29 Himax Technologies, Inc. Method for writing data into memory and the control device
CN100361049C (zh) * 2005-03-08 2008-01-09 华硕电脑股份有限公司 计算机系统及其清除控制电路和清除环境设定内存的方法
JP4068106B2 (ja) * 2005-08-05 2008-03-26 三菱電機株式会社 リアルタイム組込み簡易モニタプログラム
US7937706B2 (en) * 2005-08-22 2011-05-03 Runtime Design Automation, Inc. Method and system for performing fair-share preemption
KR100679050B1 (ko) * 2005-12-12 2007-02-06 삼성전자주식회사 태스크간 빠른 문맥 교환을 위해 레지스터 문맥을 저장,복구하는 방법 및 장치
KR100663709B1 (ko) * 2005-12-28 2007-01-03 삼성전자주식회사 재구성 아키텍처에서의 예외 처리 방법 및 장치
KR100681199B1 (ko) * 2006-01-11 2007-02-09 삼성전자주식회사 코어스 그레인 어레이에서의 인터럽트 처리 방법 및 장치
US8125243B1 (en) 2007-03-12 2012-02-28 Cypress Semiconductor Corporation Integrity checking of configurable data of programmable device
WO2009022371A1 (ja) 2007-08-16 2009-02-19 Netcleus Systems Corporation タスク処理装置
US20110072247A1 (en) * 2009-09-21 2011-03-24 International Business Machines Corporation Fast application programmable timers
KR20150002129A (ko) * 2013-06-28 2015-01-07 에스케이하이닉스 주식회사 반도체 장치, 그를 포함하는 반도체 시스템 및 그 반도체 시스템의 테스트 방법
KR20170065845A (ko) 2015-12-04 2017-06-14 삼성전자주식회사 프로세서 및 제어 방법
US9971516B2 (en) 2016-10-17 2018-05-15 International Business Machines Corporation Load stall interrupt
CN108874517B (zh) * 2018-04-19 2021-11-02 华侨大学 固定优先级待机备用系统利用率划分能耗优化方法
CN111506531B (zh) * 2020-03-27 2023-06-02 上海赛昉科技有限公司 一种easy-master微码模块及其配置方法

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Also Published As

Publication number Publication date
US5987601A (en) 1999-11-16
CA2320913A1 (en) 1999-08-19
NO20004043L (no) 2000-10-11
CN1293776A (zh) 2001-05-02
HK1036663A1 (en) 2002-01-11
KR20060024029A (ko) 2006-03-15
KR100635519B1 (ko) 2006-10-17
KR100647526B1 (ko) 2006-11-23
KR100617357B1 (ko) 2006-08-28
CA2320913C (en) 2008-10-14
US6981133B1 (en) 2005-12-27
NO20004043D0 (no) 2000-08-11
KR20010040959A (ko) 2001-05-15
EP1062572A1 (en) 2000-12-27
JP2002503845A (ja) 2002-02-05
KR20060031883A (ko) 2006-04-13
MXPA00007850A (es) 2002-08-20
WO1999041661A1 (en) 1999-08-19
TW448366B (en) 2001-08-01
EP1062572A4 (en) 2003-06-25
CN1116639C (zh) 2003-07-30
ID26818A (id) 2001-02-15
AU2659899A (en) 1999-08-30

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2069 DE 31/08/2010.

B15K Others concerning applications: alteration of classification

Ipc: G06F 9/46 (2006.01)