DE60221094D1 - Erzeugung sequentieller Test-Muster mit einer prüfgerecht konzipierten Taktsignal-Kontrolle - Google Patents

Erzeugung sequentieller Test-Muster mit einer prüfgerecht konzipierten Taktsignal-Kontrolle

Info

Publication number
DE60221094D1
DE60221094D1 DE60221094T DE60221094T DE60221094D1 DE 60221094 D1 DE60221094 D1 DE 60221094D1 DE 60221094 T DE60221094 T DE 60221094T DE 60221094 T DE60221094 T DE 60221094T DE 60221094 D1 DE60221094 D1 DE 60221094D1
Authority
DE
Germany
Prior art keywords
test
generation
clock control
sequential
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60221094T
Other languages
English (en)
Other versions
DE60221094T2 (de
Inventor
Miron Abramovici
Yu Xiaoming
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of DE60221094D1 publication Critical patent/DE60221094D1/de
Application granted granted Critical
Publication of DE60221094T2 publication Critical patent/DE60221094T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
DE60221094T 2002-03-26 2002-08-14 Erzeugung sequentieller Test-Muster mit einer prüfgerecht konzipierten Taktsignal-Kontrolle Expired - Lifetime DE60221094T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US106960 2002-03-26
US10/106,960 US7017096B2 (en) 2002-03-26 2002-03-26 Sequential test pattern generation using clock-control design for testability structures

Publications (2)

Publication Number Publication Date
DE60221094D1 true DE60221094D1 (de) 2007-08-23
DE60221094T2 DE60221094T2 (de) 2008-03-20

Family

ID=27804359

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60221094T Expired - Lifetime DE60221094T2 (de) 2002-03-26 2002-08-14 Erzeugung sequentieller Test-Muster mit einer prüfgerecht konzipierten Taktsignal-Kontrolle

Country Status (4)

Country Link
US (1) US7017096B2 (de)
EP (1) EP1348972B1 (de)
JP (1) JP4024707B2 (de)
DE (1) DE60221094T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US7263675B2 (en) * 2004-06-03 2007-08-28 Synopsys, Inc. Tuple propagator and its use in analysis of mixed clock domain designs
US7360185B2 (en) * 2005-02-03 2008-04-15 International Business Machines Corporation Design verification using sequential and combinational transformations
US20060236185A1 (en) * 2005-04-04 2006-10-19 Ronald Baker Multiple function results using single pattern and method
US7231571B2 (en) * 2005-04-28 2007-06-12 Yardstick Research, L.L.C. Single-pass methods for generating test patterns for sequential circuits
WO2006123204A1 (en) 2005-05-19 2006-11-23 Freescale Semiconductor, Inc. Method and device for high speed testing of an integrated circuit
US7958421B2 (en) 2007-08-16 2011-06-07 Yardstick Research, Llc Single-pass, concurrent-validation methods for generating test patterns for sequential circuits
US8156395B2 (en) * 2008-07-28 2012-04-10 Yardstick Research, Llc Methods for generating test patterns for sequential circuits
US8843872B1 (en) * 2013-03-15 2014-09-23 Synopsys, Inc. Automatic clock tree synthesis exceptions generation
CN104316867B (zh) * 2014-10-20 2017-04-12 安徽建筑大学 高性能测试向量生成方法及生成器
KR102549438B1 (ko) * 2016-09-27 2023-06-29 삼성전자주식회사 순차 회로, 이를 포함하는 스캔 체인 회로 및 집적 회로
CN108021975A (zh) * 2017-11-15 2018-05-11 天津大学 基于基因算法的集成电路抗故障攻击能力评估方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3812337A (en) * 1973-04-06 1974-05-21 Gte Automatic Electric Lab Inc Sequential control circuit having improved fault detection and diagnostic capabilities
US4331952A (en) * 1980-09-22 1982-05-25 American District Telegraph Company Redundant sensor adapter
US5590135A (en) 1991-11-20 1996-12-31 Lucent Technologies Inc. Testing a sequential circuit
US5519713A (en) * 1993-12-02 1996-05-21 The University Of Texas System Integrated circuit having clock-line control and method for testing same
US5566187A (en) 1994-09-14 1996-10-15 Lucent Technologies Inc. Method for identifying untestable faults in logic circuits
US5559811A (en) 1994-09-14 1996-09-24 Lucent Technologies Inc. Method for identifying untestable and redundant faults in sequential logic circuits.
US5625630A (en) 1996-04-24 1997-04-29 Lucent Technologies Inc. Increasing testability by clock transformation
US5805608A (en) * 1996-10-18 1998-09-08 Samsung Electronics Co., Ltd. Clock generation for testing of integrated circuits
US6691266B1 (en) * 1999-10-15 2004-02-10 Triscend Corporation Bus mastering debugging system for integrated circuits
US6728917B2 (en) * 2001-02-09 2004-04-27 Agere Systems Inc. Sequential test pattern generation using combinational techniques
US6515530B1 (en) * 2001-10-11 2003-02-04 International Business Machines Corporation Dynamically scalable low voltage clock generation system

Also Published As

Publication number Publication date
EP1348972B1 (de) 2007-07-11
US7017096B2 (en) 2006-03-21
JP4024707B2 (ja) 2007-12-19
DE60221094T2 (de) 2008-03-20
EP1348972A2 (de) 2003-10-01
US20030188245A1 (en) 2003-10-02
EP1348972A3 (de) 2004-06-16
JP2004048664A (ja) 2004-02-12

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