DE60217884D1 - Verfahren und apparat für verteilten direktspeicherzugriff in einem system auf einem chip - Google Patents

Verfahren und apparat für verteilten direktspeicherzugriff in einem system auf einem chip

Info

Publication number
DE60217884D1
DE60217884D1 DE60217884T DE60217884T DE60217884D1 DE 60217884 D1 DE60217884 D1 DE 60217884D1 DE 60217884 T DE60217884 T DE 60217884T DE 60217884 T DE60217884 T DE 60217884T DE 60217884 D1 DE60217884 D1 DE 60217884D1
Authority
DE
Germany
Prior art keywords
direct memory
memory access
bus
access
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60217884T
Other languages
English (en)
Other versions
DE60217884T2 (de
Inventor
Kumar Ganapathy
Ruban Kanapathippillai
Saurin Shah
George Moussa
F Philhower
Ruchir Shah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60217884D1 publication Critical patent/DE60217884D1/de
Application granted granted Critical
Publication of DE60217884T2 publication Critical patent/DE60217884T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE60217884T 2001-09-07 2002-08-30 Verfahren und apparat für verteilten direktspeicherzugriff in einem system auf einem chip Expired - Lifetime DE60217884T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/949,461 US6874039B2 (en) 2000-09-08 2001-09-07 Method and apparatus for distributed direct memory access for systems on chip
US949461 2001-09-07
PCT/US2002/027642 WO2003023625A1 (en) 2001-09-07 2002-08-30 Method and apparatus for distributed direct memory access for systems on chip

Publications (2)

Publication Number Publication Date
DE60217884D1 true DE60217884D1 (de) 2007-03-15
DE60217884T2 DE60217884T2 (de) 2007-11-08

Family

ID=25489127

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60217884T Expired - Lifetime DE60217884T2 (de) 2001-09-07 2002-08-30 Verfahren und apparat für verteilten direktspeicherzugriff in einem system auf einem chip

Country Status (8)

Country Link
US (6) US6874039B2 (de)
EP (1) EP1430405B1 (de)
KR (1) KR100801763B1 (de)
CN (1) CN1552028B (de)
AT (1) ATE352814T1 (de)
DE (1) DE60217884T2 (de)
TW (1) TWI268426B (de)
WO (1) WO2003023625A1 (de)

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US7155541B2 (en) 2006-12-26
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US20020038393A1 (en) 2002-03-28
US7970961B2 (en) 2011-06-28
US20090070513A1 (en) 2009-03-12
US20130138877A1 (en) 2013-05-30
CN1552028B (zh) 2011-11-30
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US6874039B2 (en) 2005-03-29
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US20050216613A1 (en) 2005-09-29
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US8386665B2 (en) 2013-02-26
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US8719465B2 (en) 2014-05-06

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