DE60215513D1 - Zweischicht-hartmask zum ätzverfahren eines edram-gates - Google Patents

Zweischicht-hartmask zum ätzverfahren eines edram-gates

Info

Publication number
DE60215513D1
DE60215513D1 DE60215513T DE60215513T DE60215513D1 DE 60215513 D1 DE60215513 D1 DE 60215513D1 DE 60215513 T DE60215513 T DE 60215513T DE 60215513 T DE60215513 T DE 60215513T DE 60215513 D1 DE60215513 D1 DE 60215513D1
Authority
DE
Germany
Prior art keywords
edram
gate
processing
layer hardmask
hardmask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60215513T
Other languages
English (en)
Other versions
DE60215513T2 (de
Inventor
Mark Dobuzinsky
Ali Khan
C Liu
Paul Wensley
Chienfan Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60215513D1 publication Critical patent/DE60215513D1/de
Publication of DE60215513T2 publication Critical patent/DE60215513T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE60215513T 2001-08-07 2002-08-06 Zweischichthartmaske zum ätzverfahren eines edram-gates Expired - Lifetime DE60215513T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/924,118 US6518151B1 (en) 2001-08-07 2001-08-07 Dual layer hard mask for eDRAM gate etch process
US924118 2001-08-07
PCT/EP2002/008784 WO2003015132A2 (en) 2001-08-07 2002-08-06 Dual layer hard mask for edram gate etch process

Publications (2)

Publication Number Publication Date
DE60215513D1 true DE60215513D1 (de) 2006-11-30
DE60215513T2 DE60215513T2 (de) 2007-07-05

Family

ID=25449729

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60215513T Expired - Lifetime DE60215513T2 (de) 2001-08-07 2002-08-06 Zweischichthartmaske zum ätzverfahren eines edram-gates

Country Status (5)

Country Link
US (1) US6518151B1 (de)
EP (1) EP1415338B1 (de)
DE (1) DE60215513T2 (de)
TW (1) TW556270B (de)
WO (1) WO2003015132A2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7125775B1 (en) * 2004-03-18 2006-10-24 Integrated Device Technology, Inc. Method for forming hybrid device gates
US7153780B2 (en) * 2004-03-24 2006-12-26 Intel Corporation Method and apparatus for self-aligned MOS patterning
US7259107B2 (en) * 2005-02-22 2007-08-21 Infineon Technologies Ag Method of forming isolated features of semiconductor devices
US7482270B2 (en) * 2006-12-05 2009-01-27 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same
US7737049B2 (en) * 2007-07-31 2010-06-15 Qimonda Ag Method for forming a structure on a substrate and device
KR20090128902A (ko) * 2008-06-11 2009-12-16 크로스텍 캐피탈, 엘엘씨 이중 하드마스크막을 이용한 씨모스이미지센서 제조 방법
US8143699B2 (en) * 2009-02-25 2012-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Dual-dielectric MIM capacitors for system-on-chip applications
US8367508B2 (en) 2010-04-09 2013-02-05 International Business Machines Corporation Self-aligned contacts for field effect transistor devices
US9812336B2 (en) * 2013-10-29 2017-11-07 Globalfoundries Inc. FinFET semiconductor structures and methods of fabricating same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886410A (en) * 1996-06-26 1999-03-23 Intel Corporation Interconnect structure with hard mask and low dielectric constant materials
JP4404972B2 (ja) * 1998-03-30 2010-01-27 株式会社東芝 半導体記憶装置の製造方法
US6037222A (en) 1998-05-22 2000-03-14 Taiwan Semiconductor Manufacturing Company Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology
TW428311B (en) 1998-08-25 2001-04-01 United Microelectronics Corp Manufacturing method for embedded DRAM
JP3869128B2 (ja) * 1998-09-11 2007-01-17 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6153459A (en) * 1998-11-16 2000-11-28 United Microelectronics Corp. Method of fabricating dual gate structure of embedded DRAM
JP3895069B2 (ja) * 1999-02-22 2007-03-22 株式会社東芝 半導体装置とその製造方法
US6077738A (en) * 1999-06-25 2000-06-20 Taiwan Semiconductor Manufacturing Company Inter-level dielectric planarization approach for a DRAM crown capacitor process
US6168984B1 (en) * 1999-10-15 2001-01-02 Taiwan Semiconductor Manufacturing Company Reduction of the aspect ratio of deep contact holes for embedded DRAM devices
US6117730A (en) * 1999-10-25 2000-09-12 Advanced Micro Devices, Inc. Integrated method by using high temperature oxide for top oxide and periphery gate oxide
JP4530552B2 (ja) * 2001-01-29 2010-08-25 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US6518151B1 (en) 2003-02-11
EP1415338B1 (de) 2006-10-18
WO2003015132A3 (en) 2003-11-20
DE60215513T2 (de) 2007-07-05
WO2003015132A2 (en) 2003-02-20
TW556270B (en) 2003-10-01
WO2003015132A9 (en) 2004-02-19
US20030032269A1 (en) 2003-02-13
EP1415338A2 (de) 2004-05-06

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