DE602008004267D1 - Phasenregelkreis - Google Patents

Phasenregelkreis

Info

Publication number
DE602008004267D1
DE602008004267D1 DE602008004267T DE602008004267T DE602008004267D1 DE 602008004267 D1 DE602008004267 D1 DE 602008004267D1 DE 602008004267 T DE602008004267 T DE 602008004267T DE 602008004267 T DE602008004267 T DE 602008004267T DE 602008004267 D1 DE602008004267 D1 DE 602008004267D1
Authority
DE
Germany
Prior art keywords
oscillator
output
signal
generating
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602008004267T
Other languages
English (en)
Inventor
Michael Story
Nicolas Sornin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies International Ltd
Original Assignee
Cambridge Silicon Radio Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Silicon Radio Ltd filed Critical Cambridge Silicon Radio Ltd
Publication of DE602008004267D1 publication Critical patent/DE602008004267D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C5/00—Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H04L27/361—Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE602008004267T 2007-09-13 2008-08-19 Phasenregelkreis Active DE602008004267D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0717883A GB2452748A (en) 2007-09-13 2007-09-13 Digital phase locked loop
PCT/EP2008/060847 WO2009033918A1 (en) 2007-09-13 2008-08-19 Phase locked loop

Publications (1)

Publication Number Publication Date
DE602008004267D1 true DE602008004267D1 (de) 2011-02-10

Family

ID=38658915

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602008004267T Active DE602008004267D1 (de) 2007-09-13 2008-08-19 Phasenregelkreis

Country Status (7)

Country Link
US (1) US8723607B2 (de)
EP (1) EP2188895B1 (de)
CN (1) CN101849359B (de)
AT (1) ATE493796T1 (de)
DE (1) DE602008004267D1 (de)
GB (1) GB2452748A (de)
WO (1) WO2009033918A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8509371B2 (en) * 2009-09-29 2013-08-13 Analog Devices, Inc. Continuous-rate clock recovery circuit
CN102571078B (zh) * 2010-12-24 2017-04-12 北京普源精电科技有限公司 用于电气隔离和时钟同步的电路及多通道信号发生装置
US8773181B2 (en) 2012-11-30 2014-07-08 Cambridge Silicon Radio, Ltd. Locked loop circuits and methods
US10790832B2 (en) 2018-03-22 2020-09-29 Intel Corporation Apparatus to improve lock time of a frequency locked loop

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789996A (en) * 1988-01-28 1988-12-06 Siemens Transmission Systems, Inc. Center frequency high resolution digital phase-lock loop circuit
US5539351A (en) * 1994-11-03 1996-07-23 Gilsdorf; Ben Circuit and method for reducing a gate volage of a transmission gate within a charge pump circuit
US5991914A (en) * 1996-02-15 1999-11-23 Nec Corporation Clock recovery using maximum likelihood sequence estimation
US6203757B1 (en) * 1998-12-02 2001-03-20 Bionike, Inc. Fluid sample distriution system for test device
US6326851B1 (en) * 2000-06-26 2001-12-04 Texas Instruments Incorporated Digital phase-domain PLL frequency synthesizer
US6809598B1 (en) * 2000-10-24 2004-10-26 Texas Instruments Incorporated Hybrid of predictive and closed-loop phase-domain digital PLL architecture
JP4064338B2 (ja) * 2003-12-10 2008-03-19 松下電器産業株式会社 デルタシグマ型分数分周ｐｌｌシンセサイザ
CN1815892B (zh) * 2005-01-31 2011-09-28 瑞昱半导体股份有限公司 一种检测相位误差并产生控制信号的电路
US7279988B1 (en) * 2005-03-17 2007-10-09 Rf Micro Devices, Inc. Digital frequency locked loop and phase locked loop frequency synthesizer
US7330060B2 (en) * 2005-09-07 2008-02-12 Agere Systems Inc. Method and apparatus for sigma-delta delay control in a delay-locked-loop
US7801262B2 (en) 2005-10-19 2010-09-21 Texas Instruments Incorporated All digital phase locked loop architecture for low power cellular applications

Also Published As

Publication number Publication date
US20100301961A1 (en) 2010-12-02
GB2452748A (en) 2009-03-18
CN101849359A (zh) 2010-09-29
EP2188895B1 (de) 2010-12-29
ATE493796T1 (de) 2011-01-15
GB0717883D0 (en) 2007-10-24
WO2009033918A1 (en) 2009-03-19
CN101849359B (zh) 2013-09-18
EP2188895A1 (de) 2010-05-26
US8723607B2 (en) 2014-05-13

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