DE602007013438D1 - Verfahren zur bereitstellung optimaler einsatzortprogrammierung von elektronischen schmelzverbindungen - Google Patents

Verfahren zur bereitstellung optimaler einsatzortprogrammierung von elektronischen schmelzverbindungen

Info

Publication number
DE602007013438D1
DE602007013438D1 DE602007013438T DE602007013438T DE602007013438D1 DE 602007013438 D1 DE602007013438 D1 DE 602007013438D1 DE 602007013438 T DE602007013438 T DE 602007013438T DE 602007013438 T DE602007013438 T DE 602007013438T DE 602007013438 D1 DE602007013438 D1 DE 602007013438D1
Authority
DE
Germany
Prior art keywords
customer
fuse programming
optimum use
providing optimum
optimal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007013438T
Other languages
German (de)
English (en)
Inventor
Michael Richard Ouellette
Troy Joseph Perry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/555,323 external-priority patent/US7518899B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE602007013438D1 publication Critical patent/DE602007013438D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Powder Metallurgy (AREA)
DE602007013438T 2006-11-01 2007-10-17 Verfahren zur bereitstellung optimaler einsatzortprogrammierung von elektronischen schmelzverbindungen Active DE602007013438D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/555,323 US7518899B2 (en) 2006-11-01 2006-11-01 Method of providing optimal field programming of electronic fuses
US11/850,477 US7791972B2 (en) 2006-11-01 2007-09-05 Design structure for providing optimal field programming of electronic fuses
PCT/EP2007/061109 WO2008052885A1 (en) 2006-11-01 2007-10-17 Method of providing optimal field programming of electronic fuses

Publications (1)

Publication Number Publication Date
DE602007013438D1 true DE602007013438D1 (de) 2011-05-05

Family

ID=38969791

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007013438T Active DE602007013438D1 (de) 2006-11-01 2007-10-17 Verfahren zur bereitstellung optimaler einsatzortprogrammierung von elektronischen schmelzverbindungen

Country Status (7)

Country Link
US (1) US7791972B2 (cg-RX-API-DMAC7.html)
EP (1) EP2078304B1 (cg-RX-API-DMAC7.html)
JP (1) JP4659119B2 (cg-RX-API-DMAC7.html)
KR (1) KR101055917B1 (cg-RX-API-DMAC7.html)
AT (1) ATE503251T1 (cg-RX-API-DMAC7.html)
DE (1) DE602007013438D1 (cg-RX-API-DMAC7.html)
WO (1) WO2008052885A1 (cg-RX-API-DMAC7.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8028924B2 (en) * 2009-09-15 2011-10-04 International Business Machines Corporation Device and method for providing an integrated circuit with a unique identification
US8719648B2 (en) 2011-07-27 2014-05-06 International Business Machines Corporation Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture
US8537627B2 (en) 2011-09-01 2013-09-17 International Business Machines Corporation Determining fusebay storage element usage
US10598703B2 (en) 2015-07-20 2020-03-24 Eaton Intelligent Power Limited Electric fuse current sensing systems and monitoring methods
JP6207670B1 (ja) * 2016-05-24 2017-10-04 三菱電機株式会社 ワンタイムメモリの制御装置
US10223531B2 (en) 2016-12-30 2019-03-05 Google Llc Secure device state apparatus and method and lifecycle management
US10523048B2 (en) * 2018-02-16 2019-12-31 Monolithic Power Systems, Inc. Power supply and power supplying method with power backup and power sharing
US10855174B2 (en) * 2018-02-16 2020-12-01 Monolithic Power Systems, Inc. Power supply and power supply method with power sharing and overshoot preventing
US10892637B2 (en) * 2018-02-16 2021-01-12 Monolithic Power Systems, Inc. Power supply and power supplying method with power backup
US11289298B2 (en) 2018-05-31 2022-03-29 Eaton Intelligent Power Limited Monitoring systems and methods for estimating thermal-mechanical fatigue in an electrical fuse
US11143718B2 (en) 2018-05-31 2021-10-12 Eaton Intelligent Power Limited Monitoring systems and methods for estimating thermal-mechanical fatigue in an electrical fuse

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268911A (en) 1979-06-21 1981-05-19 Fairchild Camera And Instrument Corp. ROM Program security circuits
JPS5736497A (en) * 1980-08-14 1982-02-27 Toshiba Corp Semiconductor integrated circuit
JPS5936497A (ja) 1982-08-23 1984-02-28 Mitsuyoshi Sangyo Kk 音響機器の前面に装着するプラスチツクグリル枠に金属グリルを取付ける方法
US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6483736B2 (en) 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6437653B1 (en) 2000-09-28 2002-08-20 Sun Microsystems, Inc. Method and apparatus for providing a variable inductor on a semiconductor chip
US6876594B2 (en) * 2002-12-26 2005-04-05 Texas Instruments Incorporated Integrated circuit with programmable fuse array
GB0419465D0 (en) * 2004-09-02 2004-10-06 Cavendish Kinetics Ltd Method and apparatus for programming and reading codes
US20060136858A1 (en) 2004-12-17 2006-06-22 International Business Machines Corporation Utilizing fuses to store control parameters for external system components
JP2008097696A (ja) * 2006-10-11 2008-04-24 Elpida Memory Inc 半導体装置

Also Published As

Publication number Publication date
WO2008052885A1 (en) 2008-05-08
US20080104551A1 (en) 2008-05-01
EP2078304B1 (en) 2011-03-23
EP2078304A1 (en) 2009-07-15
US7791972B2 (en) 2010-09-07
JP2010508654A (ja) 2010-03-18
ATE503251T1 (de) 2011-04-15
JP4659119B2 (ja) 2011-03-30
KR20090068322A (ko) 2009-06-26
KR101055917B1 (ko) 2011-08-09

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