DE60128380D1 - Dynamische einstellung für einen spannungshub - Google Patents

Dynamische einstellung für einen spannungshub

Info

Publication number
DE60128380D1
DE60128380D1 DE60128380T DE60128380T DE60128380D1 DE 60128380 D1 DE60128380 D1 DE 60128380D1 DE 60128380 T DE60128380 T DE 60128380T DE 60128380 T DE60128380 T DE 60128380T DE 60128380 D1 DE60128380 D1 DE 60128380D1
Authority
DE
Germany
Prior art keywords
dynamic adjustment
tension hub
hub
tension
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60128380T
Other languages
English (en)
Other versions
DE60128380T2 (de
Inventor
Andrew Volk
Warren Morrow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60128380D1 publication Critical patent/DE60128380D1/de
Publication of DE60128380T2 publication Critical patent/DE60128380T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005Modifications of input or output impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Networks Using Active Elements (AREA)
DE60128380T 2000-09-29 2001-09-26 Dynamische einstellung für einen spannungshub Expired - Lifetime DE60128380T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/677,117 US6693450B1 (en) 2000-09-29 2000-09-29 Dynamic swing voltage adjustment
US677117 2000-09-29
PCT/US2001/030266 WO2002027930A2 (en) 2000-09-29 2001-09-26 Dynamic swing voltage adjustment

Publications (2)

Publication Number Publication Date
DE60128380D1 true DE60128380D1 (de) 2007-06-21
DE60128380T2 DE60128380T2 (de) 2008-01-10

Family

ID=24717401

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60128380T Expired - Lifetime DE60128380T2 (de) 2000-09-29 2001-09-26 Dynamische einstellung für einen spannungshub

Country Status (9)

Country Link
US (1) US6693450B1 (de)
EP (1) EP1327305B1 (de)
KR (1) KR20030034225A (de)
CN (1) CN100568732C (de)
AU (1) AU2002212982A1 (de)
DE (1) DE60128380T2 (de)
HK (1) HK1053751A1 (de)
TW (1) TW544993B (de)
WO (1) WO2002027930A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633178B2 (en) * 2001-09-28 2003-10-14 Intel Corporation Apparatus and method for power efficient line driver
US6842035B2 (en) 2002-12-31 2005-01-11 Intel Corporation Apparatus and method for bus signal termination compensation during detected quiet cycle
JP4144523B2 (ja) * 2003-12-26 2008-09-03 セイコーエプソン株式会社 不意の書き込みを抑制する記憶装置を備える消耗品容器
TWI271032B (en) * 2004-04-06 2007-01-11 Samsung Electronics Co Ltd Output drivers having adjustable swing widths during test mode operation
DE102005009491A1 (de) * 2005-02-24 2006-08-31 Volkswagen Ag Transceiver für ein Steuergerät
KR100575006B1 (ko) * 2005-04-12 2006-04-28 삼성전자주식회사 Ocd 회로와 odt 회로를 제어할 수 있는 반도체 장치및 제어 방법
KR100666177B1 (ko) * 2005-09-30 2007-01-09 삼성전자주식회사 모드 레지스터 셋트를 이용하여 초기강화 드라이버의 임피던스 및 강도를 제어하는 출력 드라이버
US7590392B2 (en) * 2005-10-31 2009-09-15 Intel Corporation Transmitter compensation
US7466174B2 (en) 2006-03-31 2008-12-16 Intel Corporation Fast lock scheme for phase locked loops and delay locked loops
US7567096B2 (en) * 2007-03-21 2009-07-28 Qualcomm Incorporated Circuit device and method of controlling a voltage swing
KR100938879B1 (ko) * 2007-06-28 2010-01-27 주식회사 애트랩 접촉 감지 센서 및 이 센서의 자동 감도 조절방법
US8207754B2 (en) * 2009-02-24 2012-06-26 Stmicroelectronics International N.V. Architecture for efficient usage of IO
TWI451224B (zh) * 2011-12-21 2014-09-01 Anpec Electronics Corp 動態電壓調整裝置及相關輸電系統
US9753479B2 (en) * 2012-08-01 2017-09-05 Qualcomm Incorporated Multi-standard, automatic impedance controlled driver with supply regulation
WO2014138081A1 (en) * 2013-03-05 2014-09-12 Silicon Image, Inc. Calibration of single-ended high-speed interfaces
US9537479B2 (en) * 2013-12-16 2017-01-03 Intel Corporation Programmable impedance transmitter for serial communication
US9490775B2 (en) 2014-12-19 2016-11-08 International Business Machines Corporation Implementing adaptive control for optimization of pulsed resonant drivers
US9548734B1 (en) * 2015-12-26 2017-01-17 Intel Corporation Smart impedance matching for high-speed I/O
CN113381823B (zh) * 2021-06-09 2022-08-12 北京集睿致远科技有限公司 一种发送系统输出电压幅度校准电路及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134311A (en) 1990-06-07 1992-07-28 International Business Machines Corporation Self-adjusting impedance matching driver
FR2709217B1 (fr) 1993-08-19 1995-09-15 Bull Sa Procédé et dispositif d'adaptation d'impédance pour un émetteur et/ou récepteur, circuit intégré et système de transmission les mettant en Óoeuvre.
US5677639A (en) 1994-12-08 1997-10-14 Seagate Technology, Inc. Autonomous selection of output buffer characteristics as determined by load matching
US6060907A (en) * 1997-06-25 2000-05-09 Sun Microsystems, Inc. Impedance control circuit
JPH11145814A (ja) 1997-11-07 1999-05-28 Toshiba Corp 半導体集積回路
US6118310A (en) * 1998-11-04 2000-09-12 Agilent Technologies Digitally controlled output driver and method for impedance matching
US6177809B1 (en) * 1999-05-28 2001-01-23 International Business Machines Corporation Redundant input/output driver circuit

Also Published As

Publication number Publication date
TW544993B (en) 2003-08-01
EP1327305B1 (de) 2007-05-09
CN1466816A (zh) 2004-01-07
WO2002027930A3 (en) 2002-05-16
EP1327305A2 (de) 2003-07-16
AU2002212982A1 (en) 2002-04-08
US6693450B1 (en) 2004-02-17
CN100568732C (zh) 2009-12-09
DE60128380T2 (de) 2008-01-10
WO2002027930A2 (en) 2002-04-04
KR20030034225A (ko) 2003-05-01
HK1053751A1 (en) 2003-10-31

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