DE60119350D1 - Methode zur Herstellung von Leiterbahnstrukturen - Google Patents

Methode zur Herstellung von Leiterbahnstrukturen

Info

Publication number
DE60119350D1
DE60119350D1 DE60119350T DE60119350T DE60119350D1 DE 60119350 D1 DE60119350 D1 DE 60119350D1 DE 60119350 T DE60119350 T DE 60119350T DE 60119350 T DE60119350 T DE 60119350T DE 60119350 D1 DE60119350 D1 DE 60119350D1
Authority
DE
Germany
Prior art keywords
printed conductor
conductor structures
producing printed
producing
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60119350T
Other languages
English (en)
Other versions
DE60119350T2 (de
Inventor
Stefaan Bruneel
Backer Eddy De
Malik Masgutovic Fatkhoutdinov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AMI Semiconductor Belgium BVBA
Original Assignee
AMI Semiconductor Belgium BVBA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AMI Semiconductor Belgium BVBA filed Critical AMI Semiconductor Belgium BVBA
Application granted granted Critical
Publication of DE60119350D1 publication Critical patent/DE60119350D1/de
Publication of DE60119350T2 publication Critical patent/DE60119350T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE60119350T 2001-12-17 2001-12-17 Methode zur Herstellung von Leiterbahnstrukturen Expired - Lifetime DE60119350T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01403275A EP1320128B1 (de) 2001-12-17 2001-12-17 Methode zur Herstellung von Leiterbahnstrukturen

Publications (2)

Publication Number Publication Date
DE60119350D1 true DE60119350D1 (de) 2006-06-08
DE60119350T2 DE60119350T2 (de) 2007-03-15

Family

ID=8183028

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60119350T Expired - Lifetime DE60119350T2 (de) 2001-12-17 2001-12-17 Methode zur Herstellung von Leiterbahnstrukturen

Country Status (3)

Country Link
US (1) US6835644B2 (de)
EP (1) EP1320128B1 (de)
DE (1) DE60119350T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7140374B2 (en) 2003-03-14 2006-11-28 Lam Research Corporation System, method and apparatus for self-cleaning dry etch
US7232766B2 (en) * 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US6939796B2 (en) 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US20060063388A1 (en) * 2004-09-23 2006-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for using a water vapor treatment to reduce surface charge after metal etching

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4501061A (en) * 1983-05-31 1985-02-26 Advanced Micro Devices, Inc. Fluorine plasma oxidation of residual sulfur species
JPH04311033A (ja) * 1991-02-20 1992-11-02 Micron Technol Inc 半導体デバイスのエッチング後処理方法
JPH06204191A (ja) * 1992-11-10 1994-07-22 Sony Corp 金属プラグ形成後の表面処理方法
KR19980064028A (ko) * 1996-12-12 1998-10-07 윌리엄비.켐플러 금속의 사후 에칭 탈플루오르 저온 공정
US6093658A (en) * 1997-12-22 2000-07-25 Philips Electronics North America Corporation Method for making reliable interconnect structures
US6153531A (en) * 1997-12-22 2000-11-28 Philips Electronics North America Corporation Method for preventing electrochemical erosion of interconnect structures
US6077762A (en) * 1997-12-22 2000-06-20 Vlsi Technology, Inc. Method and apparatus for rapidly discharging plasma etched interconnect structures
US6613681B1 (en) * 1998-08-28 2003-09-02 Micron Technology, Inc. Method of removing etch residues
US6410417B1 (en) * 1998-11-05 2002-06-25 Promos Technologies, Inc. Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer
US6852636B1 (en) * 1999-12-27 2005-02-08 Lam Research Corporation Insitu post etch process to remove remaining photoresist and residual sidewall passivation
US6562416B2 (en) * 2001-05-02 2003-05-13 Advanced Micro Devices, Inc. Method of forming low resistance vias
US6583046B1 (en) * 2001-07-13 2003-06-24 Advanced Micro Devices, Inc. Post-treatment of low-k dielectric for prevention of photoresist poisoning

Also Published As

Publication number Publication date
US20030148602A1 (en) 2003-08-07
EP1320128B1 (de) 2006-05-03
DE60119350T2 (de) 2007-03-15
US6835644B2 (en) 2004-12-28
EP1320128A1 (de) 2003-06-18

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Legal Events

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