DE60116972D1 - Methode für den Entwurf eines Taktungsplans - Google Patents

Methode für den Entwurf eines Taktungsplans

Info

Publication number
DE60116972D1
DE60116972D1 DE60116972T DE60116972T DE60116972D1 DE 60116972 D1 DE60116972 D1 DE 60116972D1 DE 60116972 T DE60116972 T DE 60116972T DE 60116972 T DE60116972 T DE 60116972T DE 60116972 D1 DE60116972 D1 DE 60116972D1
Authority
DE
Germany
Prior art keywords
design
timing plan
timing
plan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60116972T
Other languages
English (en)
Other versions
DE60116972T2 (de
Inventor
Noriyuki Ito
Ryoichi Yamashita
Yoichiro Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE60116972D1 publication Critical patent/DE60116972D1/de
Application granted granted Critical
Publication of DE60116972T2 publication Critical patent/DE60116972T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE60116972T 2001-07-12 2001-11-06 Verfahren zum Entwerfen von Zeitablaufbudgets Expired - Lifetime DE60116972T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001211556 2001-07-12
JP2001211556A JP3953756B2 (ja) 2001-07-12 2001-07-12 タイミングバジェット設計方法

Publications (2)

Publication Number Publication Date
DE60116972D1 true DE60116972D1 (de) 2006-04-13
DE60116972T2 DE60116972T2 (de) 2006-08-10

Family

ID=19046845

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60116972T Expired - Lifetime DE60116972T2 (de) 2001-07-12 2001-11-06 Verfahren zum Entwerfen von Zeitablaufbudgets

Country Status (5)

Country Link
US (1) US6684374B2 (de)
EP (1) EP1276060B1 (de)
JP (1) JP3953756B2 (de)
KR (1) KR100704577B1 (de)
DE (1) DE60116972T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL159223A0 (en) * 2001-06-08 2004-06-01 Magma Design Automation Inc Method for generating design constraints for modules in a hierarchical integrated circuit design system
US6836874B2 (en) * 2002-06-26 2004-12-28 Agilent Technologies, Inc. Systems and methods for time-budgeting a complex hierarchical integrated circuit
JP2005149273A (ja) * 2003-11-18 2005-06-09 Matsushita Electric Ind Co Ltd 半導体集積回路のフロアプラン装置及びフロアプラン方法
US7213223B2 (en) * 2004-11-19 2007-05-01 Lsi Logic Corporation Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism
US7263678B2 (en) * 2005-03-15 2007-08-28 Lsi Corporation Method of identifying floorplan problems in an integrated circuit layout
JP4294000B2 (ja) * 2005-03-24 2009-07-08 富士通株式会社 クロック遅延解析装置、クロック遅延解析方法、クロック遅延解析プログラム、および記録媒体
WO2007017933A1 (ja) * 2005-08-09 2007-02-15 Fujitsu Limited 遅延時間表示方法、その装置、及びプログラム
US8504978B1 (en) * 2009-03-30 2013-08-06 Cadence Design Systems, Inc. User interface for timing budget analysis of integrated circuit designs
US9098661B1 (en) * 2008-12-10 2015-08-04 The Mathworks, Inc. Extensible platform for back-annotation of target-specific characterization onto a model of a hardware system
JP5564231B2 (ja) * 2009-10-16 2014-07-30 株式会社日立情報通信エンジニアリング Ｌｓｉ設計方法及びプログラム
US8397197B1 (en) * 2011-05-25 2013-03-12 Applied Micro Circuits Corporation Integrated circuit module time delay budgeting
CN105447215B (zh) * 2014-09-24 2018-07-27 瑞昱半导体股份有限公司 数字电路设计方法及相关的系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
US5222030A (en) * 1990-04-06 1993-06-22 Lsi Logic Corporation Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
US5648913A (en) * 1993-03-29 1997-07-15 Xilinx, Inc. Frequency driven layout system and method for field programmable gate arrays
US5903472A (en) * 1996-10-25 1999-05-11 Advanced Micro Devices, Inc. Method for performing floorplan timing analysis by selectively displaying signal paths based on slack time calculations and integrated circuit made using same
JP3662149B2 (ja) * 1998-10-08 2005-06-22 株式会社東芝 リピータ・セルの配置方法、その配置装置、および記録媒体
JP2000187676A (ja) * 1998-12-22 2000-07-04 Mitsubishi Electric Corp 論理合成装置および論理合成プログラムを記録したコンピュータ読み取り可能な記録媒体
JP2001142922A (ja) * 1999-11-15 2001-05-25 Matsushita Electric Ind Co Ltd 半導体集積回路装置の設計方法
US6415426B1 (en) * 2000-06-02 2002-07-02 Incentia Design Systems, Inc. Dynamic weighting and/or target zone analysis in timing driven placement of cells of an integrated circuit design

Also Published As

Publication number Publication date
DE60116972T2 (de) 2006-08-10
EP1276060A3 (de) 2003-09-24
US6684374B2 (en) 2004-01-27
JP3953756B2 (ja) 2007-08-08
KR100704577B1 (ko) 2007-04-06
KR20030006900A (ko) 2003-01-23
US20030014720A1 (en) 2003-01-16
JP2003030267A (ja) 2003-01-31
EP1276060B1 (de) 2006-02-01
EP1276060A2 (de) 2003-01-15

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8328 Change in the person/name/address of the agent

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