DE60116744D1 - Verfahren zur herstellung eines elektrischen verbindungselements und elektrisches verbindungselement - Google Patents

Verfahren zur herstellung eines elektrischen verbindungselements und elektrisches verbindungselement

Info

Publication number
DE60116744D1
DE60116744D1 DE60116744T DE60116744T DE60116744D1 DE 60116744 D1 DE60116744 D1 DE 60116744D1 DE 60116744 T DE60116744 T DE 60116744T DE 60116744 T DE60116744 T DE 60116744T DE 60116744 D1 DE60116744 D1 DE 60116744D1
Authority
DE
Germany
Prior art keywords
connecting element
producing
electric
electrical
electrical connecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60116744T
Other languages
English (en)
Other versions
DE60116744T2 (de
Inventor
Walter Schmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dyconex AG
Original Assignee
Dyconex AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dyconex AG filed Critical Dyconex AG
Application granted granted Critical
Publication of DE60116744D1 publication Critical patent/DE60116744D1/de
Publication of DE60116744T2 publication Critical patent/DE60116744T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0379—Stacked conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path
DE60116744T 2000-03-31 2001-03-30 Verfahren zur herstellung eines elektrischen verbindungselements und elektrisches verbindungselement Expired - Lifetime DE60116744T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US19337000P 2000-03-31 2000-03-31
US193370P 2000-03-31
PCT/CH2001/000204 WO2001080612A1 (en) 2000-03-31 2001-03-30 Method for fabricating electrical connecting element, and electrical connecting element

Publications (2)

Publication Number Publication Date
DE60116744D1 true DE60116744D1 (de) 2006-04-06
DE60116744T2 DE60116744T2 (de) 2006-08-31

Family

ID=42830456

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60116744T Expired - Lifetime DE60116744T2 (de) 2000-03-31 2001-03-30 Verfahren zur herstellung eines elektrischen verbindungselements und elektrisches verbindungselement

Country Status (5)

Country Link
US (1) US6954986B2 (de)
EP (1) EP1269807B1 (de)
AU (1) AU2001242207A1 (de)
DE (1) DE60116744T2 (de)
WO (1) WO2001080612A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI297095B (en) * 2003-10-02 2008-05-21 Au Optronics Corp Bonding pad structure for a display and fabrication method thereof
JP5105168B2 (ja) * 2005-11-02 2012-12-19 イビデン株式会社 多層プリント配線板
JP4811015B2 (ja) * 2005-12-21 2011-11-09 イビデン株式会社 プリント配線板の製造方法
US7523545B2 (en) * 2006-04-19 2009-04-28 Dynamic Details, Inc. Methods of manufacturing printed circuit boards with stacked micro vias
US7557304B2 (en) * 2006-11-08 2009-07-07 Motorola, Inc. Printed circuit board having closed vias
US7427562B2 (en) * 2006-11-08 2008-09-23 Motorla, Inc. Method for fabricating closed vias in a printed circuit board
JP2009200356A (ja) * 2008-02-22 2009-09-03 Tdk Corp プリント配線板及びその製造方法
JP5161617B2 (ja) * 2008-03-03 2013-03-13 日本メクトロン株式会社 フレキシブル回路基板、及びその製造方法
JP2010118635A (ja) * 2008-11-12 2010-05-27 Ibiden Co Ltd 多層プリント配線板
US8020292B1 (en) 2010-04-30 2011-09-20 Ddi Global Corp. Methods of manufacturing printed circuit boards
CN104409364B (zh) * 2014-11-19 2017-12-01 清华大学 转接板及其制作方法、封装结构及用于转接板的键合方法
US20190357364A1 (en) * 2018-05-17 2019-11-21 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With Only Partially Filled Thermal Through-Hole
CN112004321B (zh) * 2020-08-07 2021-12-03 北京浪潮数据技术有限公司 一种电路板上表贴连接器的设计方法及电路板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3346950A (en) * 1965-06-16 1967-10-17 Ibm Method of making through-connections by controlled punctures
DE2050160A1 (de) * 1969-10-13 1971-04-22 Avery Products Corp Verfahren und Vorrichtung zur Her stellung \on graphischen Matrizen
NL8403755A (nl) * 1984-12-11 1986-07-01 Philips Nv Werkwijze voor de vervaardiging van een meerlaags gedrukte bedrading met doorverbonden sporen in verschillende lagen en meerlaags gedrukte bedrading vervaardigd volgens de werkwijze.
US5121299A (en) * 1989-12-29 1992-06-09 International Business Machines Corporation Multi-level circuit structure utilizing conductive cores having conductive protrusions and cavities therein
DE19522338B4 (de) 1995-06-20 2006-12-07 Pac Tech-Packaging Technologies Gmbh Chipträgeranordnung mit einer Durchkontaktierung
WO1999049708A1 (en) * 1998-03-27 1999-09-30 Minnesota Mining And Manufacturing Company Method for making electrical connections between conductors separated by a dielectric
US6601297B1 (en) * 1998-08-28 2003-08-05 Dyconex Patente Ag Method for producing micro-openings

Also Published As

Publication number Publication date
DE60116744T2 (de) 2006-08-31
EP1269807B1 (de) 2006-01-18
AU2001242207A1 (en) 2001-10-30
EP1269807A1 (de) 2003-01-02
US20030121700A1 (en) 2003-07-03
US6954986B2 (en) 2005-10-18
WO2001080612A1 (en) 2001-10-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition