DE60107904D1 - Gerät und Verfahren zur automatischen Erzeugung von Schaltungen, und Rechnerprogrammprodukt zur Ausführung des Verfahrens - Google Patents

Gerät und Verfahren zur automatischen Erzeugung von Schaltungen, und Rechnerprogrammprodukt zur Ausführung des Verfahrens

Info

Publication number
DE60107904D1
DE60107904D1 DE60107904T DE60107904T DE60107904D1 DE 60107904 D1 DE60107904 D1 DE 60107904D1 DE 60107904 T DE60107904 T DE 60107904T DE 60107904 T DE60107904 T DE 60107904T DE 60107904 D1 DE60107904 D1 DE 60107904D1
Authority
DE
Germany
Prior art keywords
carrying
computer program
program product
automatically generating
generating circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60107904T
Other languages
English (en)
Other versions
DE60107904T2 (de
Inventor
Kimiyoshi Usami
Naoyuki Kawabe
Masahiro Kanazawa
Masayuki Koizumi
Hidemasa Zama
Toshiyuki Furusawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE60107904D1 publication Critical patent/DE60107904D1/de
Application granted granted Critical
Publication of DE60107904T2 publication Critical patent/DE60107904T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE60107904T 2000-06-29 2001-06-29 Gerät und Verfahren zur automatischen Erzeugung von Schaltungen, und Rechnerprogrammprodukt zur Ausführung des Verfahrens Expired - Lifetime DE60107904T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000197270 2000-06-29
JP2000197270A JP3853576B2 (ja) 2000-06-29 2000-06-29 回路自動生成装置、回路自動生成方法及び回路自動生成プログラムを記載した記録媒体

Publications (2)

Publication Number Publication Date
DE60107904D1 true DE60107904D1 (de) 2005-01-27
DE60107904T2 DE60107904T2 (de) 2005-12-08

Family

ID=18695616

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60107904T Expired - Lifetime DE60107904T2 (de) 2000-06-29 2001-06-29 Gerät und Verfahren zur automatischen Erzeugung von Schaltungen, und Rechnerprogrammprodukt zur Ausführung des Verfahrens

Country Status (4)

Country Link
US (1) US6493856B2 (de)
EP (1) EP1168205B1 (de)
JP (1) JP3853576B2 (de)
DE (1) DE60107904T2 (de)

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US6591407B1 (en) * 2000-03-01 2003-07-08 Sequence Design, Inc. Method and apparatus for interconnect-driven optimization of integrated circuit design
JP2002215705A (ja) * 2001-01-23 2002-08-02 Toshiba Corp 回路自動生成装置、回路自動生成方法及び回路自動生成プログラムを記録した記録媒体
JP2002299454A (ja) * 2001-04-02 2002-10-11 Toshiba Corp 論理回路設計方法、論理回路設計装置及び論理回路マッピング方法
US6718524B1 (en) * 2001-09-17 2004-04-06 Lsi Logic Corporation Method and apparatus for estimating state-dependent gate leakage in an integrated circuit
US6981231B2 (en) * 2002-02-22 2005-12-27 Hewlett-Packard Development Company, L.P. System and method to reduce leakage power in an electronic device
US6771118B2 (en) * 2002-10-30 2004-08-03 Texas Instruments Incorporated System and method for reducing a leakage current associated with an integrated circuit
US7302652B2 (en) * 2003-03-31 2007-11-27 Intel Corporation Leakage control in integrated circuits
US6910197B2 (en) * 2003-06-20 2005-06-21 Sun Microsystems, Inc. System for optimizing buffers in integrated circuit design timing fixes
US7017131B2 (en) * 2003-07-07 2006-03-21 Stmicroelectronics Limited Cell replacement algorithm
US7058908B2 (en) * 2003-08-25 2006-06-06 Hewlett-Packard Development Company, L.P. Systems and methods utilizing fast analysis information during detailed analysis of a circuit design
US20050050503A1 (en) * 2003-08-25 2005-03-03 Keller S. Brandon Systems and methods for establishing data model consistency of computer aided design tools
US7032206B2 (en) 2003-08-25 2006-04-18 Hewlett-Packard Development Company, L.P. System and method for iteratively traversing a hierarchical circuit design
US7086019B2 (en) 2003-08-25 2006-08-01 Hewlett-Packard Development Company, L.P. Systems and methods for determining activity factors of a circuit design
US7062727B2 (en) 2003-08-25 2006-06-13 Hewlett-Packard Development Company, L.P. Computer aided design systems and methods with reduced memory utilization
US20050050506A1 (en) * 2003-08-25 2005-03-03 Keller S. Brandon System and method for determining connectivity of nets in a hierarchical circuit design
US7047507B2 (en) * 2003-08-25 2006-05-16 Hewlett-Packard Development Company, L.P. System and method for determining wire capacitance for a VLSI circuit
US20050050485A1 (en) * 2003-08-25 2005-03-03 Keller S. Brandon Systems and methods for identifying data sources associated with a circuit design
US7076752B2 (en) * 2003-08-25 2006-07-11 Hewlett-Packard Development Company, L.P. System and method for determining unmatched design elements in a computer-automated design
JP3990339B2 (ja) * 2003-10-30 2007-10-10 株式会社東芝 回路自動設計装置、回路自動設計方法及び回路自動設計プログラム
JP4267476B2 (ja) * 2004-02-16 2009-05-27 株式会社東芝 半導体集積回路の設計方法、設計装置および検査装置
US7188325B1 (en) * 2004-10-04 2007-03-06 Advanced Micro Devices, Inc. Method for selecting transistor threshold voltages in an integrated circuit
US7281230B2 (en) * 2005-04-20 2007-10-09 Taiwan Semiconductor Manufacturing Company Method of using mixed multi-Vt devices in a cell-based design
US7370294B1 (en) * 2005-04-21 2008-05-06 Xilinx, Inc. Design techniques for low leakage circuits based on delay statistics
US7397271B2 (en) * 2005-08-19 2008-07-08 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US20080061848A1 (en) * 2006-09-08 2008-03-13 Arm Limited Output driver circuit having a clamped mode and an operating mode
WO2008153667A2 (en) * 2007-05-22 2008-12-18 Guy Maor Method and system for high speed and low memory footprint static timing analysis
US9411390B2 (en) 2008-02-11 2016-08-09 Nvidia Corporation Integrated circuit device having power domains and partitions based on use case power optimization
US9423846B2 (en) 2008-04-10 2016-08-23 Nvidia Corporation Powered ring to maintain IO state independent of the core of an integrated circuit device
US8607177B2 (en) * 2008-04-10 2013-12-10 Nvidia Corporation Netlist cell identification and classification to reduce power consumption
US20100107130A1 (en) * 2008-10-23 2010-04-29 International Business Machines Corporation 1xn block builder for 1xn vlsi design
KR101020291B1 (ko) * 2009-02-03 2011-03-07 주식회사 하이닉스반도체 프리드라이버 및 이를 이용한 출력드라이버회로
US8626480B2 (en) 2009-10-06 2014-01-07 International Business Machines Corporation Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
US9471395B2 (en) 2012-08-23 2016-10-18 Nvidia Corporation Processor cluster migration techniques
US8947137B2 (en) 2012-09-05 2015-02-03 Nvidia Corporation Core voltage reset systems and methods with wide noise margin
CN108957246A (zh) * 2018-09-27 2018-12-07 广东电网有限责任公司 一种基于粒子群的配电网故障定位方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5774367A (en) * 1995-07-24 1998-06-30 Motorola, Inc. Method of selecting device threshold voltages for high speed and low power
US5903577A (en) * 1997-09-30 1999-05-11 Lsi Logic Corporation Method and apparatus for analyzing digital circuits
JP3777768B2 (ja) * 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
JPH11195973A (ja) 1998-01-07 1999-07-21 Oki Electric Ind Co Ltd 半導体装置及びそれを用いた双方向光ｍｏｓリレー

Also Published As

Publication number Publication date
JP3853576B2 (ja) 2006-12-06
US6493856B2 (en) 2002-12-10
US20020002701A1 (en) 2002-01-03
JP2002015017A (ja) 2002-01-18
DE60107904T2 (de) 2005-12-08
EP1168205A2 (de) 2002-01-02
EP1168205A3 (de) 2002-06-05
EP1168205B1 (de) 2004-12-22

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